ISSCC
2001 February 4 – 8, 2001, San Francisco Marriott Hotel
Technical
Program: Monday – Wednesday, February 5 – 7
PLENARY SESSION
1.1 i-mode: 21st Century Mobile Internet
Kei-ichi Enoki, NTT DoCoMo, Tokyo, Japan
1.2 Broadband Access: the Last Mile
L. Cloetens, Alcatel, Zaventem, Belgium
1.3 Microprocessors for the New Millennium –Challenges, Opportunities and New Frontiers
Patrick P. Gelsinger, Intel Corporation, Hillsboro, OR, USA
Non Volatile Memory
2.1 A 3.3V 1Gb Multi-Level NAND Flash Memory with Non-Uniform Threshold Voltage Distribuition
Samsung Electronics, Kyunggi, Korea
2.2 A 126.6mm2 AND-Type 512Mb Flash Memory with 1.8V Power Supply
Hitachi Ltd., Tokyo,
Japan
2.3 A 1.8V 64Mb 100MHz Flexible Read while Write Flash Memory
Intel Corporation, Folsom, CA
2.4 An Embedded 1.2V read Flash Memory Module in a 0.18µm Logic Process.
Philips Research laboratories, Eindhoven, The Netherlands
2.5 A Highly-Reliable 1T1C 1Mb FRAM with Novel Ferro-Programmable Redundancy Scheme
Fujitsu Limited, Tokyo, Japan
2.6 A Nonvolatile Ferroelectric RAM with Common-Plate Folded Bit-line Cell and Enhanced Data Sensing Scheme
Samsung Electronics Co., Kyunggi, Korea
2.7 A 76mm2 8Mb Chain Ferroelectric Memory
Toshiba Corporation, Yokohama, Japan
Oversampling Converters
3.1 A 13.5mW, 185MSample/s DeltaSigma-Modulator for UMTS/GSM Dual-Standard IF Reception
Swiss Federal Institute of Technology (ETH), Zurich,
Switzerland
3.2 A 5mW SigmaDelta Modulator with 84dB Dynamic Range for GSM/EDGE
Motorola SPS, Toulouse, France
3.3 A Quadrature Data Dependent DEM Algorithm to Improve Image Rejection of a Complex SigmaDelta Modulator
Philips Research Labs, Eindhoven, The Netherlands
3.4 A 2.5V Broadband Multi-Bit SigmaDelta Modulator with 95dB Dynamic Range
Stanford University, Stanford, CA
3.5 A 1V 10.7MHz Switched-Opamp Bandpass SigmaDelta Modulator Using Double-Sampling Finite-Gain-Compensation Technique
Hong Kong University of Science & Technology, Hong Kong,
China
3.6 A Low-Power Reconfigurable Analog-to-Digital Converter
Massachusetts Institute of Technology, Cambridge, MA
High-Speed Digital Interfaces
4.1 A Serial-Link Transceiver Based on 8GSample/s A/D and D/A Converters in 0.25µm CMOS
Stanford University, Stanford, CA
4.2 A 2Gb/s 21CH Low-Latency Transceiver Circuit for Inter-Processor Communication
NEC Corp., Tokyo, Japan
4.3 3.2GHz 6.4Gb/s/wire Signaling in 0.18µm CMOS
Intel Corporation, Hillsboro, OR
4.4 5Gb/s Bidirectional Balanced-Line Link Compliant with Plesiochronous Clocking
Fujitsu Laboratories LTD., Kawasaki, Japan
4.5 A 2Gb/s/pin 4-PAM Parallel Bus Interface with Transmit Crosstalk Cancellation & Equalization and Integrating Receivers
Rambus Inc., Mountain View, CA
4.6 Digitally-Controlled DLL and I/O Circuits for 500Mb/s/pin x16 DDR SDRAM
Samsung Electronics, Kiheug, Korea
4.7 Circuit Design for a 2.2GB/s Memory Interface
Rambus Inc, Mountain View, CA
Gigabit Optical Communications
I
5.1 An Offset-Cancelled CMOS Clock Recovery/Demux with a Half-Rate Linear Phase Detector for 2.5Gb/s Optical Communication
Lucent Technologies, Holmdel, NJ
5.2 Fully-Integrated SONET OC48 Transceiver in Standard CMOS
Newport Communication, Irvine, CA
5.3 A 10Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection
UCLA, Los Angeles, CA
5.4 A 10Gb/s 16:1 Multiplexer and 10GHz Clock Synthesizer in 0.25µm SiGe BiCMOS
Lucent Technologies, Holmdel, NJ
5.5 A Single-Chip 10Gb/s Transceiver LSI using SiGe SOI/BiCMOS
Hitachi, Ltd., Yokohama, Japan
5.6 40Gb/s Clock and Data Recovery / 1:4 DEMUX IC in SiGe Technology
Lucent Technologies,
Nuremberg, Germany
CMOS Image Sensors with
Embedded Processors
6.1 A 10kframes/s 0.18µm CMOS Digital Pixel Sensor with Pixel-Level Memory
Stanford University, Stanford, CA
6.2 A Miniature Imaging Module for Mobile Applications
ST Microelectronics, Edinburgh, United Kingdom
6.3 Arbitrated Address Event Representation Digital Image Sensor
Johns Hopkins University, Baltimore, MD
6.4 A 48kframes/s CMOS Image Sensor for Real-Time 3-D Sensing and Motion Detection
Sony-Kihara Research Center, Inc., Tokyo, Japan
6.5 A 128x128 CMOS Imager with 4x128 Bit-Serial Column-Parallel PE Array
Toshiba, Yokohama, Japan
6.6 A Signal-Processing CMOS Image Sensor using a Simple Analog Operation
NEC Corporation, Kanagawa, Japan
6.7 Autoscaling CMOS APS with Customized Increase of Dynamic Range.
Ben-Gurion University, Beer-Sheva, Israel
TD: Advanced Technologies
7.1 Genetic Applets: Biological Integrated Circuits for Cellular Control
Cellicon Biotechnologies, Jamaica Plain, MA
7.2 The Design and Measurement of Molecular Electronic Switches and Memories
Yale University, New Haven, CT
7.3 Strained Si Surface Channel MOSFETS for High-Performance CMOS Technology
IBM T.J. Watson Research Center, Yorktown Heights, NY
7.4 FinFET - A Quasi-Planar Double-Gate MOSFET
University of California, Berkeley, CA
7.5 Ultra-Miniature, High-Q Filters and Duplexers Using FBAR Technology
Agilent Technologies, Newark, CA
7.6 A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM
Motorola, Tempe, AZ
Nyquist ADCs
8.1 A 6b 1.3GSample/s A/D Converter in 0.35µm CMOS
University of California Los Angeles, Los Angeles, CA
8.2 A 6b 1.1GSample/s CMOS A/D Converter
Philips Semiconductors, Eindhoven, Netherlands
8.3 A 1.8V 10b 100MSample/s CMOS Pipelined ADC
Texas Instruments, Dallas, TX
8.4 A 2.5V 12b 54MSample/s 0.25µm CMOS ADC in 1mm2
Philips Research Labs., Eindhoven, The Netherlands
8.5 A 3V 14b 75MSample/s CMOS ADC wtih 85dB SFDR at Nyquist
Analog Devices Inc., Wilmington, MA
8.6 A 14b 40MSample/s Pipelined ADC with DFCA
Texas Instruments, Dallas, TX
Integrated Multimedia
Processors
9.1 A 90mW MPEG4 Video Codec LSI with the Capability for Core Profile
Matsushita Electric Industrial Co., Fukuoka, Japan
9.2 A 80/20MHz 160mW Multimedia Processor integrated with Embedded DRAM, MPEG-4 Accelerator, and 3D Rendering Engine for Mobile Applications
KAIST, Taejon, Korea
9.3 One Chip 15frame/s Mega-Pixel Real-time Image Processor
SANYO Electric Co., Ltd., Gifu, Japan
9.4 A 250MHz Single-Chip Multiprocessor for A/V Signal Processing
Sony Corporation, Tokyo, Japan
9.5 A 4GOPS 3Way-VLIW Image Recognition Processor based on a Configurable Media-Processor
Toshiba Co., Kawasaki, Japan
9.6 A 150MHz Graphics Rendering Processor with 256Mb Embedded DRAM
Altius Solutions, Inc., Santa Clara, CA
Wireless Building Blocks I
10.1 A 1.5W Class-F RF Power Amplifier in 0.2µm CMOS Technology
Philips Semiconductors, Milpitas, CA
10.2 A CMOS RF Power Amplifier with Parallel Amplification for Efficient Power Control
Stanford University, Stanford, CA
10.3 A 1W 0.35µm CMOS Power Amplifier for GSM-1800 with 45% PAE
Nokia Denmark A/S, Copenhagen, Denmark
10.4 A 1.75GHz Highly-Integrated Narrow-Band CMOS Transmitter with Harmonic-Rejection Mixers
University of California, Berkeley, CA
10.5 A +18dBm IIP3 LNA in 0.35µm CMOS
University of Minnesota, Minneapolis, MN
10.6 A Wideband 1.3GHz PLL for Transmit Remodulation Supression
Motorola, Inc., Plantation, FL
SRAM
11.1 Universal-Vdd 0.65-2.0V 32kB Cache using Voltage-Adapted Timing-Generation Scheme and a Lithographically-Symmetrical Cell
Hitachi, Ltd., Tokyo, Japan
11.2 An Architecture for Compact Associative Memories with deca-ns Nearest-Match Capability up to Large Distances
Hiroshima University, Hiroshima, Japan
11.3 SRAM Current-Sense Amplifier with Fully-Compensated Bit Line Multiplexer
Technical University of Munich, Munich, Germany
11.4 Abnormal Leakage Suppression (ALS) Scheme for Low-Standby-Current SRAMs
University of Tokyo, Tokyo, Japan
11.5 A 900MHz 2.25MB Cache with On-Chip CPU - Now In Cu SOI
Hewlett Packard, Fort Collins, CO
Signal Processing for Storage
and Coding
12.1 Power-Efficient Application-Specific VLIW Processor for Turbo Decoding
Philips, Eindhoven, The Netherlands
12.2 A Mixed-Signal 0.18µm CMOS SOC for DVD Systems with 432MSample/s PRML Read Channel and 16Mb Embedded DRAM.
Matsushita Electric Industrial Co., LTD., Osaka, Japan
12.3 A 700Mb/s BiCMOS Read Channel Integrated Circuit
LSI Logic, San Jose, CA
12.4 A 300MHz Mixed-Signal FDTS/DFE Disk Read Channel in 0.6µm CMOS
UCLA, Los Angeles, CA
12.5 A 1Gb/s Read/Write-Preamplifier for Hard-Disk-Drive Applications
Philips, Eindhoven, The Netherlands
12.6 A 2.3GSample/s 10-tap Digital FIR Filter for Magnetic Recording Read Channels
IBM, Yorktown Heights, Yorktown, NY
12.7 A 16b Accurate CMOS Laser Driver IC with 500mA Output Current and 1.5ns Rise Time
Philips Research, Eindhoven, The Netherlands
Wireless LAN
13.1 A Fully-Integrated Single-Chip SOC for Bluetooth
Alcatel Microelectronics, Zaventem, Belgium
13.2 A Fully-Integrated CMOS RFIC for Bluetooth Applications
Institute of Microelectronics, Singapore
13.3 A 2.4GHz CMOS Transceiver for Bluetooth
Broadcom Corporation, El Segundo, CA
13.4 A 22mW Bluetooth Transceiver with Direct RF Modulation and On-chip IF Filters
Conexant Systems Inc., Nepean, ON, Canada
13.5 A Zero-IF Single-Chip Transceiver for up to 22Mb/s QPSK IEEE802.11b Wireless LAN
Philips Semiconductors, Sunnyvale, CA
13.6 A Single-Chip 2.4GHz RF Transceiver LSI with a Wide-Range FV Conversion Demodulator
Mitsubishi Electric Corp., Itami, Japan
13.7 A Fully-Integrated 5GHz CMOS Wireless-LAN Receiver
Stanford University, Center for Integrated Systems,
Stanford, CA
Gigabit Optical Communications
II
14.1 A 0.6 - 2.5GBaud CMOS Tracked 3x Oversampling Transceiver with Dead-Zone Phase Detection for Robust Clock/Data Recovery
Seoul National University, Seoul, Korea
14.2 A 2.75Gb/s CMOS Clock-Recovery Circuit with Broad Capture Range
UCLA, Los Angeles, CA
14.3 Si Bipolar Laser Driver/Receiver Chip Set for 4-Channel 5Gb/s Parallel Optical Interconnection
NEC, Kawasaki, Japan
14.4 A 1V 1mW CMOS Front-End with On-chip Dynamic Gate Biasing for a 75Mb/s Optical Receiver
Univ. of Toronto, Toronto, Canada
14.5 A Redundant Multi-Valued Logic for 10Gb/s CMOS Demultiplexer IC
NEC, Kanagawa, Japan
14.6 A Chipset for Scalable QoS-Preserving Protocol-Independent Packet Switch Fabrics
Bell Labs, Lucent Technologies, Holmdel, NJ
14.7 A 28.5GB/s CMOS Non-Blocking Router for Terabit/s Connectivity between Multiple Processors and Peripheral I/O Nodes
Intel Corporation, Hillsboro, OR
14.8 40Gb/s ASIC Switch Design Using Low-Jitter Clock Recovery
Texas Instruments, Dallas, TX
Microprocessors
15.1 A Scalable Performance 32b Microprocessor
Intel Corp., Chandler, AZ
15.2 POWER4 Physical Design
IBM, Austin, TX
15.3 A Process-Portable 64b Embedded Microprocessor with Graphics Extension and a 3.6GB/s Interface
Mips Technologies Inc., Mountain View, CA
15.4 First-Generation MAJC Dual Microprocessor
Sun Microsystems, Inc., Sunnyvale, CA
15.5 A 1.1GHz First 64b Generation S/390 Microprocessor
IBM, Poughkeepsie, NY
15.6 A 1.2GHz Alpha Microprocessor with 44.8GB/s Chip Pin Bandwidth
Compaq Computer Corporation, Shrewsbury, MA
Integrated MEMS and Display
DriverS
16.1 A CMOS Multi-Parameter Biochemical Microsensor with Temperature Control and Signal Interfacing
Siemens AG
16.2 A Single-Chip CMOS Resonant Beam Gas Sensor
ETH Zurich, Zurich, Switzerland
16.3 Integrated Hall Sensor Array Microsystem
Swiss Federal Institute of Technology, Lausanne, Switzerland
16.4 A Capacitive Fingerprint Sensor with Low-Temperature Poly-Si TFTs
Mitsubishi Electric Corp., Amagasaki, Hyogo, Japan
16.5 A CMOS Photosensor Array for 3D Imaging Using Pulsed Laser
Fraunhofer IMS Duisburg, Duisburg, Germany
16.6 A Versatile Micro-Power High-Voltage Flat Panel Display Driver
University of Gent, Gent, Belgium
16.7 100frames/s CMOS Range Image Sensor
Carnegie Mellon University, Pittsburgh, PA
TD: 3D Technologies and
Measurement Techniques
17.1 Three-Dimensional Integrated Circuits for Low-Power High-Bandwidth Systems on a Chip
MIT Lincoln Laboratory, Lexington, MA
17.2 Neuromorphic Vision Chip Fabricated Using Three-Dimensional Integration Technology
Tohoku University, Sendai, Japan
17.3 3-D Assembly Interposer Technology for Next-Generation Integrated Systems
North Corporation, Tokyo, Japan
17.4 Millimeter-Wave Characteristics of SiGe Heterojunction Bipolar Transistors and Monolithic Interconnects in Silicon Technologies
University of Toronto, Toronto, ON, Canada
17.5 Backside Infrared Probing for Static Voltage Drop and Dynamic Timing Measurements
Intel Corp., Santa Clara, CA
17.6 Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution
Georgia Institute of Technology, Atlanta, GA
17.7 Sea of Leads: A Disruptive Paradiagm for a System-on-a-Chip
Georgia Institute of Technology, Atlanta, GA
3G Wireless
18.1 A 22mA 3.7dB NF Direct Conversion Receiver for 3G WCDMA
Helsinki University of Technology, Espoo, Finland
18.2 A Fully-Integrated CMOS RF Front-End with On-Chip VCO for WCDMA Applications
Korea Advance Institute of Science and Technology, Taejon,
Korea
18.3 A 1V 12mW 2GHz Receiver with 49dB of Image Rejection in CMOS/SIMOX
NTT, Kanagawa, Japan
18.4 A 930MHz CMOS DC-Offset-Free Direct-Conversion 4-FSK Receiver
Hong Kong University of Science & Technology, Hong Kong,
China
18.5 A 900MHz Dual Conversion Low-IF GSM Receiver in 0.35µm CMOS
UCLA, Los Angeles, CA
18.6 A 2GHz CMOS Image-Reject Receiver with Sign-Sign LMS Calibration
UCLA, Los Angeles, CA
VOICEBAND, xDSL and Gigabit
Ethernet Circuits and Transceivers
19.1 A 285mW CMOS Single Chip Analog Front End for G.SHDSL
Infineon Technologies AG, Munich, Germany
19.2 A CMOS Direct Access Arrangement using Digital Capacitive Isolation
Silicon Laboratories, Inc, Austin, TX
19.3 A High-Voltage Line Driver for Combined Voice and ADSL Services
Legerity, Inc., Austin, TX
19.4 An ADSL Central Office AFE Integrating an Actively-Terminated Line Driver, Receiver, and Analog Filters
Texas Instruments, Dallas, TX
19.5 SOPA: A Highly-Efficient Line Driver in 0.35µm CMOS Using a Self-Oscillating Power Amplifier
KU Leuven, Leuven, Belgium
19.6 A DSP Based Receiver for 1000BASE-T PHY
Marvell Semiconductor, Sunnyvale, CA
19.7 A CMOS Transceiver Analog Front-end for Gigabit Ethernet over CAT-5 Cables
Marvell Semiconductor, Inc., Sunnyvale, CA
Multi-gigahertz Microprocessor
technologies
20.1 A 1.8GHz Instruction Window Buffer
IBM Entwicklung GmbH, Boeblingen, Germany
20.2 A Low-Power SOI Adder Using Reduced-Swing Charge-Recycling Circuits
Fujitsu Laboratories of America, Inc., Sunnyvale, CA
20.3 Sub-500ps 64b ALUs in 0.18µ SOI/Bulk CMOS: Design & Scaling Trends
Intel Corp., Hillsboro, OR
20.4 Design and Migration Challenges for an Alpha Microprocessor in a 0.18µm Copper Process
Compaq Computer Corp., Shrewsbury, MA
20.5 A 1GHz PA-RISC Processor
Hewlett-Packard, Fort Collins, CO
20.6 4GHz Integer Execution Unit for 0.18µm CMOS Microprocessor
Intel, Hillsboro, OR
Signal Processing for
Communications
21.1 A Universal Cable Set-Top Box System on a Chip
Broadcom Corporation, Irvine, CA
21.2 An Energy-Efficient IEEE 1363-based Reconfigurable Public-Key Cryptography Processor
Chrysalis-ITS, Ottawa, Canada
21.3 A Self-Contained 100µW Multirate FSK Receiver ASIC
UCLA, Los Angeles, CA
21.4 A Single-chip Band-Segmented-Transmission OFDM Demodulator for Digital Terrestrial Television Broadcasting
Fujitsu Laboratories LTD., Kawasaki, Japan
21.5 A Digital 72Mb/s 64-QAM OFDM Transceiver for 5GHz Wireless LAN in 0.18µm CMOS
IMEC and K.U. Leuven, Leuven, Belgium
21.6 A Single Chip PHY COFDM Modem for IEEE 802.11a with Integrated ADCs and DACs
Radiata Communications, Level 2, North Ryde, Australia
TD: System-on-a-chip
22.1 Substrate Noise Generation in Complex Digital Systems: Efficient Modeling and Simulation Methodology and Experimental Verification
IMEC, Leuven, Belgium
22.2 ChipOS: Open Power-Management Platform to Overcome the Power Crisis in Future LSIs
Hitachi, Ltd., Central Research Laboratory, Tokyo, Japan
22.3 Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data
NEC Corporation, Kanagawa, Japan
22.4 An Implementation of Two Multiprocessor DSPs: A Design Methodology Case Study
Lucent Technologies, Holmdel, NJ
22.5 A GSM 2+ Conversion Signal Processor for Continuous Full-Duplex EDGE/GPRS Applications
Lucent Technologies, Allentown, PA
22.6 A Fully-Configurable GSM BTS Controller and GMSK-EDGE Base-Band Transmitter IC
Alcatel Telecom, Antwerp, Belgium
22.7 A Multicarrier GMSK Modulator for Base Stations
Electronic Circuit Design Laboratory, Helsinki University of
Technology, Espoo, Finland
Analog Techniques
23.1 A Synchronous Dual-Output Switching dc-dc Converter Using Multibit Noise-Shaped Switch Control
Sigmatel,
Austin, TX
23.2 Dynamically Biased 1MHz Low-pass Filter with 61dB peak SNR and 112dB Input Range
Columbia
University, New York, NY
23.3 A 200nV Offset 6.5nV/rootHz Noise PSD 5.6kHz Chopper Instrumentation Amplifier in 1µm Digital CMOS
Swiss
Federal Institute of Technology (ETH), Zurich, Switzerland
23.4 A Filtering Technique to Lower Oscillator Phase Noise
UCLA,
Los Angeles, CA
23.5 A 12b 500MSample/s Current-Steering CMOS D/A Converter
K.U.
Leuven, Heverlee, Belgium
23.6 A 1.9GHz Si Active LC Filter with On-Chip Automatic Tuning
Lucent
Technologies, Murray Hill, NJ
23.7 A 0.25ìm CMOS 17GHz VCO
K.U.
Leuven, Leuven, Belgium
23.8 A 50GHz VCO in 0.25ìm CMOS
Bell
Labs, Murray Hill, NJ
23.9 A Wideband BiCMOS VCO for Multi-Mode Mobile Phones
Infineon
Technologies AG, Munich, Germany
DRAM
24.1 A 4Gb DDR SDRAM with Gain-Controlled Pre-Sensing and Reference Bitline Calibration Schemes in the Twisted Open Bitline Architecture
Samsung Electronics, Kyungki, Korea
24.2 A Multi-Gigabit DRAM Technology with 6F2 Open Bit-line Cell Distributed Over-Driven Sensing and Stacked-Flash Fuse
ELPIDA Memory.Inc.,
Tokyo, Japan
24.3 A 113mm2 600Mb/sec/pin 512Mb DDR2 SDRAM with Vertically Folded Bitline Architecture
IBM Microelectronics, Hopewell Junction, NY
24.4 A 1.0V 230MHz Column Access Embedded DRAM Macro with Dual Interface and Triple Test Functions for Portable MPEG Applications
Mitsubishi Electric Corp., Hyogo, Japan
24.5 A 1.43GHz Per Data I/O 16Mb DDR Low-Power DRAM Macro for A 3D Graphics Engine
United Memories, Inc., Colorado Springs, CO
24.6 An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced On-Chip Tester
Mitsubishi Electric Corp., Hyogo, Japan
Clock Generation and
Distribution
25.1 A 4GHz 40dB PSRR PLL for SOC Application
SiByte Inc., Santa Clara, CA
25.2 A Low-Jitter 125-1250MHz Process-Independent 0.18µm CMOS PLL Based on a Sample-Reset Loop Filter
Crystal Cirrus Logic, Austin, TX
25.3 A Low-Jitter Skew-Calibrated Multi-Phase Clock Generator for Time-Interleaved Applications
Iowa State University, Ames, IA
25.4 A 2.5GHz 4-phase Clock Generator with Scalable and No Feedback Loop Architecture
NEC Corporation, Sagamihara, Japan
25.5 Multi-GHz Low-Power Low-Skew Rotary Clock Scheme
North Carolina State University, Raleigh, NC
25.6 The Design and Analysis of the Clock Distribution Network for a 1.2GHz Alpha Microprocessor
Compaq, Shrewsbury, MA
25.7 A Multi-GHz Clocking Scheme for Pentium® 4 Microprocessor
Intel Corp, Hillsoboro, OR
Wireless Building Blocks II
26.1 A Triple-Band 900/1800/1900MHz Low-Power Image-Reject Front-End For GSM
Conexant Systems Inc., Newport Beach, CA
26.2 A 0.8dB NF ESD-Protected 9mW CMOS LNA
KU Leuven, Heverlee, Belgium
26.3 A 19GHz 0.5mW 0.35µm CMOS Frequency Divider with Shunt-Peaking Locking-Range Enhancement
California Institute of Technology, Pasadena, CA
26.4 A 2GHz Down-Converter with 600MHz 3dB Bandwidth using LO Signal Suppressing Output Buffer
Toshiba Corporation,
Kawasaki, Japan
26.5 3V GSM Base Station RF Receivers using 0.25µm BiCMOS
Bell Labs, Lucent Technologies, Murray Hill, NJ
26.6 A 2.4GHz 34mW CMOS Transceiver for Frequency-Hopping and Direct-Sequence Applications
UCLA, Los Angeles, CA
26.7 SiGe BiCMOS Broadband Phase Aligner
from 1 to 11Gb/s
Siemens AG,
Ulm, Germany
Evening Discussion Sessions
E1 Does
Fabless Mean Futureless for Imaging?
E2 10
Years of RF-CMOS - But How Many
Products Today?
E3 Has
Scaling Created a Microprocessor Monster?
E4 How Will Future Portable Systems
Store and Access Data: Disk, Semiconductor Memory, Emerging Technology, or via
the Internet?
E5 Embedded
DRAM: Curiosity or Workhorse?
E6 Broadband Access - Who Will Win
the Race: Copper, Fiber or Wireless?
E7 100cubed: Science or
Fiction? Is It Possible to Design a
100mm2 System-on-Chip with 100M Transistors in 100 Days?
E8 Are
Startups Killing Innovation?
Instructor: Yuriy M.Greshishchev,
Nortel Networks, Ottawa, Canada
Instructor: David Harris Harvey Mudd
College, Claremont, CA
Instructor: C. Bernard Shung, Allayer
Communications, San Jose, CA
Instructor: Simon Segars, ARM Inc.,
Austin, TX
Instructor: Bud Taddiken, Microtune,
Plano, TX
Instructors: Philip Alvelda,
MicroDisplay, San Pablo, CA.
Instructors:
Kai Schleupen, IBM, Yorktown Heights, NY
This
Short Course is intended to jumpstart
engineers in design and development of CMOS circuits for wireless applications.
Course completion provides an overall perspective of system tradeoffs along
with detailed circuit design strategies for key RF wireless transceiver
building blocks. Topics include overview of mobile wireless systems and key
metrics of RF design, low noise amplifier characteristics, tradeoffs and
designs, fundamentals of mixer design for RF receivers, and CMOS oscillator
circuit analysis and design.
MOBILE TRANSCEIVER DESIGN SYSTEM
OVERVIEW
Instructor: Qiuting Huang, Swiss Federal Institute of Technology (ETH),
Zurich
LOW-NOISE
AMPLIFIERS
Instructor: David Allstot, Univ.
of Washington and Mobilan Corp.
CMOS UP
AND DOWN CONVERTERS
Instructor: Michiel Steyaert, K.U. Leuven Laboratory
Instructor: Asad A Abidi, UCLA
IEEE Solid-State Circuits and Technology Committee Workshop
Coordinator: Robert Bayruns, TROPIAN
This
workshop is intended for experts in the field.
Topics tentatively planned for the Workshop are the following. For an updated agenda, please refer to the
SSCS website at www.ieee.org/ssctc.
EDGE Systems
Architectures
for 3G
3G IC Design
Power Amp
Linearization
I/Q
Modulator Impairments
3G Circuit
Design
Device
Technologies for 3G
3G Circuits
and Architectures
RF Power
Measurements
Chair - Vojin G.
Oklobdzija , University of California
This workshop on microprocessor
design discusses important technical issues and directions in design of
next-generation microprocessors. It addresses issues of high performance on a
variety of levels: architecture, circuit, power and chip-to-chip
interconnection. The workshop encourages open interchange in a closed forum.
Attendance is limited and pre-registration is required.
Introduction/Processor Design Challenges
1) SOI Circuit Design for
High-Performance CMOS Microprocessors
2) Transitioning to SOI:
Coping with the Challenges and Exploiting the Advantages
3) Design Challenges of high performance I/O
4) I/O Design Styles for High performance Microprocessors
5) Software and Hardware Schemes for Achieving Low-Power
6) Power Reducing Microarchitectural Techniques
8) Chip
Multi-Processing: Architectural Issues and Trade-Offs
9) Ideas
Behind NUMA Design
10) Workshop
Discussion