SESSION
TA 7
SALON
1-6,
Tues,
8
8:30
AM
TECHNOLOGY
DIRECTIONS:
EMERGING
MEMORY AND DEVICE TECHNOLOGIES
Chair:
B. Martino, Motorola, Austin, TX
Associate
Chair: K. Ishibashi, Hitachi, Ltd., Kokubunji, Japan
7.1 Millipede
- A Highly-Parallel Dense Scanning-Probe-
Based
Data-Storage System
8:30
AM
M.
Lutwyche, G. Cross, M. Despont, U. Drechsler, U. Dürig,
W.
Häberle, H. Rothuizen, R. Stutz, R. Widmer, G. Binnig, P. Vettiger
IBM
Zurich Research Lab, Rüschlikon, Switzerland
An
alternative approach to magnetic hard-disk drives uses a 32x32 array of
scanning probe microscopes to store data as indents in a
poly-methylmethacrylate medium. Parallel read/write results show 200Gb/in
2.
7.2 A
10ns Read and Write Non-Volatile Memory Array using a Magnetic Tunnel Junction
and FET Switch in Each Cell
9:00
AM
R.
Scheuerlein, W. Gallagher
1,
S. Parkin, A. Lee, S. Ray,
R.
Robertazzi
1,
W. Reohr
1
IBM
Almaden Research Center, San Jose, CA
1IBM
T. J. Watson Research Center, Yorktown Heights, NY
1kb
memory arrays use a magnetic tunnel junction and FET in each cell and
current-mode read and write for 10ns performance. Read and write power are 5mW
and 40mW, respectively. Cell area is 3.07
um2
in 0.25
um
CMOS.
7.3 Nonvolatile
RAM based on Magnetic Tunnel Junction Elements
9:30
AM
M.
Durlam, P. Naji, M. DeHerrera, S. Tehrani, G. Kerszykowski,
K.
Kyler
Motorola
Labs, Tempe, AZ
Magnetoresistive
elements are integrated with CMOS, exhibiting unlimited nonvolatility and
unlimited R/W endurance. Magnetic tunnel junction switching for 0.9x1.5
um2
devices is demonstrated.
BREAK 10:00
AM
7.4 Phase-State
Low-Electron-Number-Drive Random-Access Memory (PLEDM)
10:15
AM
K.
Nakazato, K. Itoh
1,
H. Ahmed
2,
H. Mizuta, T. Kisu
3,
M. Kato
4,
T.
Sakata
1
Hitachi
Cambridge Lab, Cambridge, UK
1Hitachi
Central Research Lab, Tokyo, Japan
2Cambridge
Univ., Cambridge, UK
3Hitachi
ULSI Systems Co., Tokyo, Japan
4Hitachi
Ltd., Tokyo, Japan
A
phase-state low-electron-number-drive memory (PLEDM) uses a stacked tunnel
transistor with 5F
2
cell. Simulated read and write times are 20 and 2ns, respectively. Retention
times longer than 10 years are possible.
7.5 A
Vertical Replacement-Gate (VRG) Process for Scalable General-Purpose
Complementary Logic
10:45
AM
D.
Monroe, J. Hergenrother
Bell
Labs, Lucent Technologies, Murray Hill, NJ
A
process for vertical MOSFETs has precise gate length below 50nm with current
lithography, gate oxide grown on a single-crystal silicon channel, and shallow
self-aligned source/drain extensions. This CMOS process has density comparable
to that of planar CMOS, 2x the drive current, and modest parasitics.
CONCLUSION 11:15
AM