SESSION
MP 6
SALON
10-15,
Mon.,
7
1:30
PM
IMAGE
SENSORS
Chair:
Y. Hagiwara, Sony Corp., Osaki, Tokyo, Japan
Associate
Chair: R. Etienne-Cummings, Johns Hopkins Univ.,
Baltimore,
MD
6.1 A
CMOS Image Sensor with a Simple FPN-Reduction Technology and a Hole-Accumulated
Diode
1:30
PM
K.
Yonemoto, H. Sumi, R. Suzuki, K. Shiono, T. Ueno
Sony
Corp. Atsugi-shi, Kanagawa, Japan
A
CMOS image sensor with simple fixed-pattern noise (FPN) reduction technology
and hole-accumulation-diode sensing has 0.52V/lx-s sensitivity, 200mV
saturation signal, and 370pA/cm
2
dark current at room temperature. FPN is reduced with CDS and a 5-Tr. pixel
that sequentially outputs reset and signal levels.
6.2 A
CMOS Image Sensor for High-Speed Imaging
2:00
PM
N.
Stevanovic, M. Hillebrand, B. Hosticka, A. Teuner
Fraunhofer
Inst. of Microelectronic Circuits and Systems,
Duisburg,
Germany
A
256x256 pixel imager in standard 1
um
CMOS is capable of acquiring >1000frames/s. Combination of correlated double
sampling, S&H, and a high-speed synchronous shutter enables integration
between 1-150
us.
Interleaved pipelining enables 22Mpixel/s/channel with 4 output channels. The
113mm
2
chip dissipates 320mW.
6.3 A
256x256 CMOS Differential Passive Pixel Imager with FPN Reduction Techniques
2:30
PM
I.
Fujimori, C-C. Wang, C. Sodini
Massachusetts
Inst. of Technology, Cambridge, MA
A
256x256 CMOS passive pixel imager in a differential architecture with a
correlated double-sampling output circuit removes the blooming effects of a
parasitic current that plagues passive pixels. 0.1% pixel-to-pixel and 0.4%
column-to-column fixed pattern noise are achieved.
6.4 A
60mW 10b CMOS Image Sensor with Column-to-Column FPN Reduction
2:45
PM
T.
Sugiki, S. Ohsawa, M. Hoshino, H. Miura, M. Sasaki,
N.
Nakamura, Y. Tomizawa, T. Arakawa, I. Inoue
Toshiba
Corp., Yokohama, Japan
A
60mW 10b 660(H) x 494(V) pixel digital CMOS image sensor with column-to-column
FPN reduction uses a double-inverting amplifier structure with double clamp
circuit to reduce column-to-column fixed-pattern noise. It operates with a 3.3V
supply and consumes 60mW. The sensor uses 0.6
um,
triple-poly-silicon, double-metal CMOS.
BREAK 3:00
PM
6.5 A
Progressive Scan CCD Imager for DSC Applications
3:15
PM
T.
Yamada, Y-G. Kim, H. Wakoh, T. Toma, T. Sakamoto, K. Ogawa, E. Okamoto, K.
Masukane, K. Oda
1,
M. Inuiya
1
Fuji
Film Micro Devices Co. Ltd., Kurokawa-Gun, Miyagi, Japan
1Fuji
Photo Film Co., Ltd.
A
progressive-scan CCD imager in standard double-layer polysilicon is designed on
a pixel-interleaved-array architecture. The pixel layout increases both
saturation voltage and sensitivity by a factor of 1.3. The interleaved array
increases resolution by
[radical]2x
in H & V directions.
6.6 A
1/3inch 1.3Mpixel Single-Layer Electrode CCD with High-Frame-Rate Skip Mode
3:45
PM
K.
Hatano, M. Furumiya, I. Murakami, T. Kawasaki, C. Ogawa,
Y.
Nakashiba
NEC
ULSI Device Development Lab, Sagamihara, Japan
A
1/3inch 1.3MPixel IT-CCD image sensor for digital cameras using 0.25
um-gap
1-layer poly-Si for CCD electrodes has high-frame-rate skip mode (75frames/s)
and advanced 3:1 interlace (15fields/s). Separate boron ion implants maintain
charge-transfer efficiency for V- and H-CCDs. A modified microlens with thinner
spacer layer decreases sensitivity dependence on lens aperture by 18% at f1.4.
6.7 A
1.2V Micropower CMOS Active Pixel Image Sensor for Portable Applications
4:15
PM
K.-B.
Cho
1,
2,
A. Krymski
2,
E. Fossum
2
1Univ.
of Southern California, Los Angeles, CA
2Photobit
Corp., Pasadena, CA
A
micropower 176x144 CMOS active pixel sensor (APS) with on-chip 8b ADC operates
at 20frames/s from a 1.2V power supply. The sensor core including the pixel
array, row/column logic, analog readout, and ADC, dissipates only 50
uW.
Including interface pads, which perform level conversion to 3.3V, the overall
power consumption is approximately 1mW.
CONCLUSION 4:30
PM