Univ. of California, Berkeley, CA
¹Broadcom, Corp., Irvine, CA

Heterogeneous reconfiguration enables flexible implementation of baseband wireless functions at energy levels between 50-100MIPS/mW, 8 times lower than traditional DSP processors. A 5.2x6.7mm ² prototype processor for voice compression in 0.25 um 6-metal CMOS consumes 1.8mW at 40MHz average operation rate. It combines an embedded microprocessor with an array of computational units connected by a hierarchical configurable interconnect network.

Bell Labs, Lucent Technologies, Holmdel, NJ

A multiprocessor DSP chip has four programmable processing elements and a global resource controller connected to a high-performance split-transaction bus. The 207mm ² 0.25 um CMOS chip achieves 1.6 billion 16b MAC/s at 100MHz operation with 3.3V.

Mitsubishi Electric Corp., Nagaokakyo, Japan

A complete single-chip multi- PSK demodulator for Japanese BS digital broadcasting features dynamic multi- demodulation and independent 2-channel TS outputs with low PCR jitter. The chip has 2 8b 60MHz ADCs, 58MHz VCO, 1Mb SRAM and 450k-gate FEC-demodulator core. The 8.8M-transistor chip occupies 72mm ² in 0.25 um 3-metal CMOS.

IMEC, Leuven, Belgium

A programmable transceiver for up to 80Mb/s wireless LAN in the 5GHz band with 64/128/256 subcarriers encompasses (de)framing, (I)FFT, adaptive equalization and synchronization. The 14.6mm ² 0.35 um 3.3V 50MHz CMOS IC, designed in a C++ flow, uses distributed control and clock gating to reduce power consumption.

Infineon Technologies, Villach, Austria

A 97mm ² 57MHz fully-DVB-T compliant mixed-signal single-chip COFDM-Receiver for digital television uses 0.35 um CMOS with 2.2Mb embedded DRAM. The architecture, functional blocks, analog and digital implementation details and a summary of relevant chip parameters are described.

Marvell Semiconductor Inc., Sunnyvale, CA

A commercial 500Mb/s read channel dissipating 1.2W in single-poly 0.25 um CMOS incorporates a programmable 16-state noise-predictive Viterbi detector and trellis coding. It has a signal processing gain of 3.5dB over an EPR4 channel at user bit density (UBD) 3.0 and 2.3dB at UBD 2.0.

Texas Instruments, Inc., Dallas, TX
¹University of Texas, Richardson, TX

An area-efficient low-power low-latency 550MSample/s FIR filter uses parallel architecture employing fast small multiplier based on selection of radix-8 pre-multiplied coefficients and one-hot encoded bus for compact layout and reduced power dissipation. The chip uses 0.18 um L-effective CMOS.

Bell Labs, Lucent Technologies, Holmdel, NJ

A device implements a 2-stage search algorithm for determining the best-match over a set of rules described as arbitrary ranges in 5-dimensions. Operating at 66MHz, it matches 4M packets/s against a set of 8 independent rule-bases, each with 511 rules. Several configurations that trade off throughput, number of rule sets, number of rules in each set, and external memory requirements are supported.