SESSION
MP 3
SALON
7,
Mon.,
7
1:30
PM
GIGABIT-RATE
COMMUNICATIONS
Chair:
J. Sevenhans, Alcatel, Antwerp, Belgium
Associate
Chair: M. Nettles, AMCC, San Diego, CA
3.1 A
10Gb/s Eye-Opening Monitor IC for Decision-Guided Optimization of the Frequency
Response of an Optical Receiver
1:30 PM
T.
Ellermeyer, U. Langmann, B. Wedding
1,
W. Pöhlmann
1
Ruhr
Univ., Bochum, Germany
1Alcatel
SEL AG, Stuttgart, Germany
A
single-chip eye-opening monitor is for decision-guided optimization of the
frequency response of an optical receiver. The 50GHz-f
T
SiGe IC provides an analog output voltage proportional to the horizontal eye
opening of the 2-12.5Gb/s input signal. The chip dissipates 4.95W from a -5V
supply.
3.2 A
Fully-Integrated SiGe Receiver IC for
10Gb/s
Data Rate
2:00 PM
Y.
Greshishchev, P. Schvan, J. Showell, M-L. Xu, J. Ojha, J. Rogers
Nortel
Networks, Ottawa, Ontario, Canada
A
fully-integrated receiver IC implemented in SiGe technology for 10Gb/s SONET
applications combines AGC, clock and data recovery circuit with a binary PLL,
1:8 demultiplexer and 2
7-1
PRBS generator for self-testing. The die is 4.5x4.5mm
2
and consumes 4.5W from -5V.
3.3 A
0.6W 10Gb/s SONET/SDH Bit-Error-Monitoring LSI
2:30
PM
K.
Kawai, H. Ichino
NTT
Network Innovation Labs, Yokosuka-shi, Kanagawa, Japan
A
10Gb/s SONET/SDH bit-error-monitoring LSI in Si bipolar uses byte-alligning
demux architecture based on tree-type demux and clock inversions to reduce
power to 14% that of a previously-reported chip by detecting
inversion-indicating patterns. The LSI dissipates 0.6W with -3.3V supply.
BREAK 3:00
PM
3.4 SiGe
BiCMOS 3.3V Clock and Data-Recovery Circuits for 10Gb/s Serial Transmission
Systems
3:15
PM
M.
Meghelli, B. Parker, H. Ainspan, M. Soyuer
IBM
T. J. Watson Research Ctr., Yorktown Heights, NY
9.95Gb/s
and 12.5Gb/s fully-monolithic CDR ICs in SiGe BiCMOS use a bang-bang
phase-locked loop architecture and include automatic frequency acquisition aid.
Each macro dissipates ~320mW from 3.3V supply. The 9.95Gb/s CDR exceeds OC-192
jitter tolerance specifications with 50% margin.
3.5 A
Single-Chip 3.5Gb/s CMOS/SIMOX Transceiver with Automatic-Gain-Control and
Automatic-Power-Control Circuits
3:45 PM
Y.
Ohtomo, T. Yoshida, M. Nishisaka, K. Nishimura, M. Shimaya
NTT
Telecommunications Energy Labs, Atsugi-shi, Kanagawa, Japan
A
0.20
um
CMOS/SIMOX single-chip transceiver with limiting amplifier and automatic
laser-power control operates from 0.2GHz to 3.5GHz with 2V supply. Crosstalk
noise from multiplexer/demultiplexer, word aligner, and 16B/20B encoder/decoder
is suppressed by an SOI guard ring and half-frequency clock using 50%
clock-duty PLL.
3.6 45GHz
Transimpedance 32dB Limiting Amplifier and 40Gb/s 1:4 High-Sensitivity
Demultiplexer with
Decision
Circuit using SiGe HBTs for 40Gb/s
Optical
Receiver
4:15 PM
T.
Masuda, K-i. Ohhata
1,
F. Arakawa
1,
N. Shiramizu, E. Ohue,
K.
Oda, R. Hayami, M. Tanabe
1,
H. Shimamoto
1,
M. Kondo,
T.
Harada
2,
K. Washio
Central
Research Lab, Hitachi, Ltd., Kokubunji, Tokyo, Japan
1Hitachi
Device Engineering, Co. Ltd.
2Device
Development Ctr., Hitachi, Ltd, Tokyo, Japan
A
preamplifier with 45GHz bandwidth, limiting amplifier with 32dB gain, and
40Gb/s 1:4 high-sensitivity demultiplexer with a decision circuit use SiGe HBT.
These ICs are for use in practical 40Gb/s optical receivers.
3.7 A
10Gb/s Demultiplexer IC in 0.18
um
CMOS using Current Mode Logic with Tolerance to Threshold Voltage Fluctuation
4:45 PM
A.
Tanabe
1,2,
M. Umetani
1,
I. Fujiwara
1,
T. Ogura
1,3,
K. Kataoka
1,
M.
Okihara
1,
H. Sakuraba
1,4
Tetsuo Endoh
1,4,
F. Masuoka
1,4
1Telecom.
Advancement Org. of Japan, Sendai, Miyagi, Japan
2NEC
Corp., Sagamihara, Kanagawa, Japan
3Sharp
Corp., Tenri, Nara, Japan
4Tohoku
Univ., Sendai, Miyagi, Japan
A
10Gb/s 1:8 Demultiplexer IC for optical-fiber-link systems uses 0.18
um
CMOS. The differential small-signal logic with feedback used is more tolerant
to threshold voltage fluctuation than conventional logic and is suitable for
GHz operation of deep submicron CMOS circuits.
3.8 A
1:4 Demultiplexer for 40Gb/s Fiber-Optic Applications
5:00
PM
J.
Mattia, R. Pullela, Y. Baeyens, Y. Chen, H. Tsai, G. Georgiou,
T.
Von Mohrenfels
1,
M. Reinhold
1,
C. Groepper
1,
C. Dorschky
1,
C.
Schulien
1
Bell
Labs, Lucent Technologies, Murray Hill, NJ
1Lucent
Technologies, Nuremburg, Germany
A
four-channel DEMUX for 40Gb/s fiber-optic applications uses AlInAs/InGaAs-based
HBT technology. Measurements demonstrate proper 40Gb/s operation for 0.3Vpp
single-ended data input and 0.6Vpp differential clock input.
CONCLUSION 5:15
PM