J. Cancio, T. R. Viswanathan, Texas Instruments, Warren, NJ

An ADC designed for hard-disk drive read channels provides 6b resolution at 700MSample/s with a 7b servo mode operating at 200MSample/s. Measured SNDR is 35.2dB in 6b mode and 41dB in 7b mode. The ADC occupies 0.45mm ² and consumes 187mW in 0.21 um CMOS.

Matsushita Electric Industrial Co., Ltd., Osaka, Japan

An interpolated parallel 6b 800MSample/s A/D converter in 0.25 um CMOS occupies an active area of 1.8 x 0.95mm ² and consumes 400mW. Current-steering latches with single-ended clocking are employed. Measured ENOB is >5b up to 200MHz input at 800MHz sampling.

Korea Advanced Institute of Science and Technology, Taejon, Korea

A CMOS LC oscillator in 0.6 um CMOS with a ring structure to extend phase noise performance limited by conventional LC oscillators shows -132dBc/Hz measured phase noise at 600kHz offset from a 900MHz carrier and dissipates 20mW with 2.5V supply. The phase noise enhancement through the ring structure is estimated by linear modeling.

J. Lin, Bell Labs, Lucent Technologies, Murray Hill, NJ

An integrated VCO uses an on-chip resonator in common-base configuration. Measured phase noise at 600kHz, 800kHz, and 3MHz offsets is -129dBc/Hz, -132dBc/Hz, and -148dBc/Hz, respectively. Phase noise performance meets receiver blocking requirements of DCS 1800 Micro base stations. The chip consumes 38mW and generates 3mW at 1.5GHz.

LSI Logic, Milpitas, CA

An integrated mixed-signal baseband processor IC for IS-95 contains 7.5M transistors on a 10.6mm ² die and consumes 82mA in standby and 128mA in conversion modes. The type-approved production chip integrates two DSPs, microprocessor, memory, baseband codec, voiceband codec, 11b dual-slope ADC, 10b PDM DACs, PLL, 32kHz oscillator, and sine wave squarer in 0.25 um digital CMOS.

Univ. of Toronto, Toronto, Ontario, Canada

A wide-band differential line driver for transformer-coupled cables integrated in standard 0.35 um CMOS achieves 160MHz bandwidth and no loss in implementing the cable termination. The line driver operates at 3.3V supply and exhibits a -47dB THD for a 2V _pp signal across a 75 Ohm load. Automatically-tuned termination and voltage gain independent of process and load impedance variation are provided by the architecture.

M. Ang, R. Salem, A. Taylor, Sun Microsystems Inc., Palo Alto, CA

On-chip decoupling capacitors are actively switched to suppress resonance in the power distribution system of a microprocessor. Charge storage capacity is amplified. Instantaneous monitoring of rail activity and dynamic control of the switching response provide bandlimited on-chip voltage regulation.

Philips Research Labs, Eindhoven, The Netherlands

The output of the USB-powered DC/DC converter delivers 100mA at 5V with 89% efficiency. The 3-phase up/down converter has four digitally-controlled 5V-tolerant switches. The switching frequency is ~600kHz. Only a few external components are needed. The chip area is 1.0mm ² in standard 0.35 um 3.3V CMOS.

Univ. of California, Davis, CA
¹now with Analog Devices, Inc., Wilmington, MA
²Texas Instruments, Dallas, TX

A band-gap reference uses a 0.5 um digital CMOS without resistors, and ratioed transistors biased in strong inversion together with the inverse-function for temperature-insensitive gain applied to the PTAT term in the reference. After trimming, the output voltage change from 0 to 70 ^oC is 9.4mV. It occupies 0.4mm ² and dissipates 1.4mW from a 3.7V supply.