SESSION
WP 25
SALON
9,
Wed,
9
1:30
PM
NEXT-GENERATION
MICROPROCESSORS
Chair:
S. Naffziger, Hewlett Packard, Fort Collins, CO
Associate
Chair: A. Scherer, Advanced Micro Devices,
Sunnyvale,
CA
25.1 The
Architecture of a 3rd Generation 64b SPARC Microprocessor
1:30 PM
M.
Boffey, J. Chamdani, D. Chen, D. Chiacchia, D. Greenley,
K.
Holdbrook, B. Keish, G. Lauterbach, A. Leung, H. Lopez,
W.
Lynch, R. Melanson, C. Narasimhaiah, J. Petolino, L. Quach,
K.
Tam, K. Yau
Sun
Microsystems, Palo Alto, CA
A
third-generation 600MHz quad-issue 64b SPARC microprocessor for desktop
workstations, work-group server and enterprise server platforms includes
on-chip 64kB 4-way associative data cache, 32kB 4-way associative instruction
cache, 2kB 4-way associative prefetch cache and 2kB 4-way associative
write-cache. The chip uses a 0.18
um
7-layer metal process with 23M transistors.The chip consumption <80W from
1.8V.
25.2 Implementation
of a 3rd-Generation SPARC
V9
64b Microprocessor
2:00 PM
K.
Aingaran, M. Ang, M. Boland, A. Das, P. Dixit, G. Gouldsberry,
J.
Hart, R. Heald, T. Horel, W.-J. Hsu, J. Kaku, C. Kim, E. Kim, S. Kim, F. Klass,
H. Kwan, R. Lo, H. McIntyre, A. Mehta, D. Murata, S. Nguyen, Y-P. Pai, S.
Patel, K. Shin, S. Vishwanthaiah, G. Yee, H. You
Sun
Microsystems Inc., Palo Alto, CA
Performance
of a third-generation superscalar SPARC V9 processor is improved over previous
processors by increasing clock frequency and by improvements in the on-chip
memory system. The chip operates at 600MHz, dissipates <80W from a 1.8V
supply and contains 23M transistors (12M in RAMs) on a 370mm
2
die.
25.3 A
450MHz 64b RISC Processor using
Multiple
Threshold
Voltage CMOS
2:30 PM
T.
Yamashita, N. Yoshida
1,
M. Sakamoto, T. Matsumoto, M. Kusunoki, H. Takahashi, A. Wakahara, T. Ito, T.
Shimizu, K. Kurita, K. Higeta,
K.
Mori, N. Tamba, N. Kato
2,
K. Miyamoto
3,
R. Yamagata
3,
H. Tanaka
3,
T. Hiyama
3
Hitachi
Ltd, Device Development Ctr., Tokyo, Japan
1Hitachi
ULSI Engineering Co., Tokyo, Japan
2Central
Research Lab, Tokyo, Japan
3Enterprise
Server Div., Kanagawa, Japan
A
450MHz 64b RISC processor for server occupies 18.5x18.5mm
2
and contains 8.3M logic transistors and 20M RAM transistors. A 0.25
um
CMOS with Lg=0.2
um,
tox=4nm, Vdd=1.8V with 7-layer metal technology is used. Multiple-threshold
voltage design is used for minimum standby current.
BREAK 3:00
PM
25.4 A
200MHz Digital Communications Processor 3:15 PM
G.
Giacalone, T. Brightman, A. Brown, J. Brown, J. Farrell, R. Fortino, T, Franco,
A. Funk, K. Gillespie, E. Gould, D. Husak, E. McLellan,
B.
Peregoy, D. Priore, M. Sankey, P. Stropparo, J. Wise
C-Port
Corp., North Andover, MA
A
programmable, MIMD digital communications processor operates at 200MHz and
contains 17 RISC cores, 32 serial data processors, 96kB of instruction memory,
192kB of data memory, and a fabric port processor. The 2.51cm
2
die contains 56M transistors and dissipates a maximum of 24W at 2.5V supply.
25.5 A
1GIPS 1W Single-Chip Tightly-Coupled Four-Way Multiprocessor with Architecture
Support for Multiple Control Flow Execution
3:45 PM
N.
Nishi, T. Inoue, M. Nomura, S. Matsushita, S. Torii, A. Shibayama, J. Sakai, T.
Ohsawa, Y. Nakamura, S. Shimada, Y. Ito, M. Edahiro,
K.-i.
Minami, O. Matsuo, H. Inoue, T. Manabe, T. Horiuchi,
M.
Motomura, M. Yamashina, M. Fukuma
NEC
Corp., Miyamae-ku, Kanagawa, Japan
A
125MHz 1GIPS 1.3V 1W microprocessor is for media/human interface applications.
With single-chip multiprocessor technology, the MPU fully utilizes multiple
control flow parallelism executing both fine and speculative threads with
compiler-based automatic parallelization. The MPU integrates 14M transistors in
10.5mm
2
die in 0.15
um
CMOS.
25.6 An
Experimental 1000-MIPS/W Microprocessor using Speed-Adaptive Threshold-Voltage
CMOS with Forward Bias
4:15 PM
M.
Miyazaki, G. Ono, T. Hattori, K. Shiozawa, K. Uchiyama,
K.
Ishibashi
Hitachi,
Ltd., Tokyo, Japan
Substrate
bias continuously controlled from -1.5V (backward) to 0.5V (forward)
compensates fabrication, supply, and temperature variation. A speed-adaptive
threshold-voltage CMOS with forward bias is used in a 4.3M-transistor
microprocessor. The 320x400
um2
generator draws 4mA. 0.3V forward body bias raises operating frequency 10%. The
320MIPS processor dissipates 170-230mW at 1.4 - 1.6V with >1000MIPS/W.
25.7 The
First-Generation IA-64 Microprocessor
4:45 PM
G.
Singer, S. Rusu
Intel
Corp., Santa Clara, CA
This
microprocessor implements the IA-64 architecture, and provides binary
compatibilty with the IA-32 instruction set. The device contains 25.4M
transistors. The chip is manufactured in a 0.18
um
CMOS with 6 metal layers and is packaged in a 1012-pad organic land grid array
using C4 assembly technology.
CONCLUSION 5:15
PM