SESSION
WP 24
SALON
8,
Wed,
9
1:30
PM
DRAM
Chair:
T-S. Jung, Samsung Electronics, Yongin-City,
Kyungki-Do,
Korea
Associate
Chair: D. Stark, Rambus, Inc., Mountain View, CA
24.1 An
8ns Random Cycle Embedded RAM Macro with Dual-Port Interleaved DRAM
Architecture (D
2RAM)
1:30
PM
Y.
Agata, K. Motomochi, Y Kagenishi, Y. Fukushima, M. Shirahama, M. Kurumada, N.
Kuroda, H. Sadakata, K. Hayashi, T. Yamada,
K.
Takahashi, T. Fujita
Matsushita
Electric Industrial Co., Nagaokakyo, Japan
An
embedded RAM macro with dual-port interleaved DRAM (D
2RAM)
has 8ns random cycle with open bit lines, time domain shielded bit line, and
2-stage pipeline.
24.2 A
56.8GB/s 0.18
um
Embedded DRAM Macro with Dual Port Sense Amplifier for 3D Graphics Controller
2:00
PM
A.
Yamazaki, T. Fujino, K. Inoue, I. Hayashi, H. Noda, N. Watanabe, F. Morishita,
J. Ootani, M. Kobayashi
1,
K. Dosaka, Y. Morooka,
H.
Shimano, S. Soeda, A. Hachisuka, Y. Okumura, K. Arimoto,
S.
Wake, H. Ozaki
Mitsubishi
Electric Corp., Itami Hyogo, Japan
1Daioh
Electric Corp., Itami, Hyogo, Japan
A
23.3mm
2
32Mb embedded DRAM macro uses 0.18
um
triple-well 4-metal embedded DRAM technology to realize 3D graphics with 32b
true color. Row access is 11.6ns at 2.0V with 2-cycle column latency at 222MHz.
24.3 1GHz
Fully-Pipelined 3.7ns Address Access Time 8kx1024 Embedded DRAM Macro
2:30 PM
O.
Takahashi, S. Dong, M. Ohkubo
1,
S. Onishi
1,
R. Dennard
2,
R.
Hannon
3,
S. Crowder
3,
S. Iyer
3,
M. Wordeman
3,
B. Davari
3
IBM
Austin Research Lab, Austin, TX
1IBM
Japan Yasu Tech. Applic. Lab, Shiga, Japan
2IBM
T. J. Watson Research Center, Yorktown Heights, NY
3IBM
Microelectronics, East Fishkill, NY
A
19.4mm
2
embedded DRAM macro runs at 1GHz at 85
oC,
-10% VDD, and nominal process. It uses a 0.18
um
L
drawn
logic-based DRAM technology, copper lines, 3-well, two oxide thicknesses, and
trench capacitors.
BREAK 3:00
PM
24.4 A
16MB Cache DRAM LSI with Internal 35.8GB/s Memory Bandwidth for Simultaneous
Read-Write
Operation
3:15 PM
M.
Nakayama, H. Sakakibara, M. Kusunoki, K. Kurita, Y. Yokoyama, S. Miyaoka, J-i.
Koike, N. Tamba, T. Kobayashi, M. Kume
1,
H.
Sawamoto
1,
A. Kawata
1,
H. Tanaka
1,
Y. Takada
1,
M. Yamamoto
1,
M.
Yagyu
2,
Y. Tsuchiya
3,
H. Yoshida
3,
N. Kitamura
3,
K. Yamaguchi
3
Hitachi,
Ltd., Device Development Ctr. /
1Enterprise
Server Div. /
2
Central
Research Lab, Tokyo, Japan
3Hitachi
ULSI Systems Co., Ltd., Tokyo, Japan
A
16MB cache DRAM has internal 35.8GB/s memory bandwidth and 9.0ns DRAM random
access and is realized using a 0.2
um
merged logic DRAM process.
24.5 New
Architecture for Cost-Efficient
High-Performance
Multiple-Bank RDRAM
3:45 PM
H.
Mukai, T. Nagai, S. Takase, S. Imai, H. Maejima, M. Ito,
T.
Yamamoto, H. Waki, K. Sakurai, T. Hara, M. Koyanagi, K. Nakagawa
Microelectronics
Engineering Lab, Toshiba Corp., Yokohama, Japan
A
288Mb RDRAM uses 0.175
um
CMOS to achieve interleaved operation of 2x16 split dependent banks with 2GB/s
data rate. It features dual page size of 1KB and 2KB, and shared data
transmission system among all banks to improve area efficiency.
24.6 A
0.18
um
256Mb DDR-SDRAM with Low-Cost
Post-Mold-Tuning
Method for DLL Replica
4:15 PM
S.
Kuge, T. Kato, K. Furutani, S. Kikuda, K. Mitsui, T. Hamamoto,
J.
Setogawa, K. Hamade, Y. Komiya, S. Kawasaki, T. Kono, T. Amano, T. Kubo, M.
Haraguchi, Z. Kawaguchi, Y. Nakaoka
1,
M. Akiyama
2,
Y.
Konishi, H. Ozaki
Mitsubishi
Electric Corp, ULSI Devel. Ctr., Itami, Hyogo, Japan
1Daioh
Electric, Itami, Hyogo, Japan
2Mitsubishi
Electric Engineering, Itami, Hyogo, Japan
A
200MHz DDR-SDRAM has a wide-range DLL. Post-mold-tuning allows precise replica
tuning after mold. Data bus achieves 400Mb/s/pin transfer.
24.7 A
500Mb/s Quadruple-Data-Rate SDRAM Interface using a Skew Cancellation Technique
4:45 PM
J.
Kim, S-H. Wang, J. Lee, H-S. Nam, Y-G. Kim, J-H. Shim, H. Ahn, S. Kang, K-N. Park
1,
B-H. Jeong
1,
J-H. Ahn
1,
B. Kim
Korea
Advanced Institute of Science and Technology, Taejon, Korea
1Hyundai
MicroElectronics Co. Ltd, Cheongju, Korea
A
quadruple data rate (QDR) SDRAM I/O interface uses salient skew cancellation.
Cancellation reduces skews between data lines on PCB to 250ps.
24.8 Antifuse
EPROM Circuit for
Field-Programmable
DRAM
5:00 PM
J-S.
Choi, J-K. Wee, P-J. Kim, J-K. Oh, C-H. Lee, H-Y. Cho,
J-Y.
Chung, S-C. Kim, W. Yang
1
Hyundai
Electronics Industries, Inchon, Korea
1Harvard
Univ., Cambridge, MA
An
antifuse EPROM with 3V programming is incorporated into a 64Mb SDRAM. The EPROM
enables post-packaging field-programmable DRAM features.
CONCLUSION 5:15
PM