SESSION
WP 22
SALON
1-6,
Wed,
9
1:30
PM
TECHNOLOGY
DIRECTIONS:
LOW-POWER
AND DIGITAL TECHNIQUES
Chair:
K. Bernstein, IBM Microelectronics, Essex Junction, VT
Associate
Chair: J. Van der Spiegel, Univ. of Pennsylvania,
Philadelphia,
PA
22.1 A
Micropower Programmable DSP Powered using a MEMS-Based Vibration-to-Electric
Energy Converter
1:30
PM
R.
Amirtharajah, S. Meninger, J. Mur-Miranda, A. Chandrakasan,
J.
Lang
Massachusetts
Inst. of Technology, Cambridge, MA
An
ultra-low-power DSP achieves six orders of magnitude lower energy compared to
existing low-power processors. It uses variable precision arithmetic,
low-voltage circuits and conditional clocks to operate using only 560nW at 1.5V V
dd
in standard 0.6
um
3-metal CMOS. Low-energy operation enables self-powered operation using ambient
vibrations. A MEMS transducer and conversion IC convert vibrations to electric
energy.
22.2 Two-Phase
Non-Overlapping Clock Adiabatic
Differential
Cascode Voltage Switch Logic (ADCVSL)
2:00
PM
D.
Suvakovic, C. Salama
Univ.
of Toronto, Toronto, Ontario, Canada
Adiabatic
differential cascode voltage switch logic (ADCVSL) operates from a two-phase
non-overlapping power clock. A non-pipelined 5x5b ADCVSL multiplier in 0.5
um
CMOS on SOI and powered from a 1V 50MHz adiabatic supply consumes 1.5pJ per
computation.
22.3 On-Chip
Multi-GHz Clocking with Transmission Lines
2:30
PM
M.
Mizuno, K. Anjo, Y. Sumi
1,
H. Wakabayashi, T. Mogami,
T.
Horiuchi, M. Yamashina
NEC
Corp, Sagamihara, Japan
1NEC
Informatec Systems, Ltd.
A
100mm
2
0.1
um
CMOS 5GHz transmission-line clocking network test chip has 20ps clock skew,
high immunity to process and supply-voltage variations, and 66% dynamic power
reduction.
BREAK 3:00
PM
22.4 Delay
Variablilty: Sources, Impacts and Trends
3:15
PM
S.
R. Nassif
IBM
Austin Research Lab, Austin, TX
Until
recently, it was sufficient to model process-induced variations as intra-die
shifts in device performance. In deep sub-micron CMOS however, within-die wire
and device variations are comparable to die-to-die variations. Historical
trends in device and wire variability are examined.
Guidance
is offered in incorporating variability into design strategy.
22.5 DS-CDMA
Wired Bus with Simple Interconnection Topology for Parallel Processing System
LSIs
3:45
PM
R.
Yoshimura, T. B. Keat, T. Ogawa, S. Hatanaka, T. Matsuoka,
K.
Taniguchi
Osaka
Univ., Suita, Japan
A
direct sequence code division multiple access (DS-CDMA) wired bus for parallel
processing has advantages over a conventional data bus: (1) simple
interconnection topology, (2) dynamic flexiblity, (3) multiple data transfer,
(4) low power dissipation. The DS-CDMA wired bus can be replaced with the
interface of conventional LSIs because of compatibility with traditional buses.
The bus interface uses ~100 x 100
um2
in 0.6
um
2-poly 3-metal CMOS.
22.6 IC
Identification Circuit using Device Mismatch
4:15
PM
K.
Lofstrom, W. Daasch
1,
D. Taylor
1
SiidTech,
Beaverton, OR
1Portland
State Univ., Portland, OR
Repeatable
binary identification is produced from random threshold mismatch in an array of
addressable MOSFETs and an auto-zeroing comparator. The analog technique is
applicable to any digital or analog submicron CMOS process, without special
processing or after-fabrication programming. Experimental devices use 0.35
um
1-poly 2-metal n-well process.
CONCLUSION 4:45
PM