SESSION
WA 21
SALON
10-15,
Wed,
9
8:30
AM
MIXED-SIGNAL
TECHNIQUES
Chair:
G. Uehara, Univ. of Hawaii, Honolulu, HI
Associate
Chair: S. Sutardja, Marvell Semiconductor Inc.,
Sunnyvale,
CA
21.1 A
Mixed Digital-Analog 16b Microcontroller with 0.5Mb Flash Memory On-Chip Power
Supply Physical Network Interface and 40V I/O for Automotive
Single-Chip
Mechatronics
8:30 AM
J.
Specks, P. Broderick, R. Erckert, J. Kruecken, H. Harb
Motorola,
Munich, Germany
A
microcontroller for mechatronic single-chip packaging includes a 16b
microcontroller with 0.5Mb flash programmable memory and CAN communication
controller analog I/O peripherals. 0.65
um
CMOS extended for high voltage requires only two more masks. The 88mm
2
1.8M-transistor chip is specified for a silicon temperature range -40
oC
to+125
oC,
and can be directly powered from the 14V car net.
21.2 A
1GHz Portable Digital Delay-Locked Loop with Infinite Phase Capture Ranges
9:00 AM
K.
Minami, M. Mizuno, H. Yamaguchi, T. Nakano, Y. Matsushima,
Y.
Sumi
1,
T. Sato
2,
H. Yamashida, M. Yamashina
NEC
Corp. Sagamihara, Japan
1NEC
Informatec Systems, Ltd, Kanagawa, Japan
2NEC
Engineering Ltd., Tokyo, Japan
A
1GHz portable digital DLL with infinite phase capture ranges use master-slave
architecture, wave-synchronous latch, and dynamic phase detector. The DLL
occupies 800x400
um2
in 0.15
um
3-layer metal CMOS. Peak-to-peak jitter with quiet supply is 29ps at 1GHz.
21.3 A
330MHz Low-Jitter and Fast-Locking Direct Skew Compensation DLL
9:30 AM
S-H.
Han, J-H. Lee, H-J. Yoo
Korea
Advanced Inst. of Science and Technology, Taejon, Korea
A
DLL with small phase difference for high-speed interfaces employs direct skew
compensation. A digital-to-time converter/time-to-digital converter compensates
initial phase difference and an analog voltage-controlled delay line
compensates remaining phase difference. A prototype in 0.4
um
SDRAM technology adds 5ps jitter to the clock source of 150ps peak-to-peak
jitter. Lock-in is <10 cycles over 150-350MHz.
BREAK 10:00
AM
21.4 A
23mW 256-Tap 8MSample/s QPSK Matched Filter for DS-CDMA Cellular Telephony
using Recycling Integrator Correlators
10:15
AM
D.
Senderowicz, S. Azuma
1,
H. Matsui
1,
K. Hara
1,
S. Kawama
1,
Y.
Ohta
1,
M. Miyamoto
1,
K. Iizuka
1
SynchroDesign
Inc., Berkeley, CA
1Sharp
Corp., Tenri, Nara, Japan
A
256-tap 8MSample/s QPSK matched filter for a DS-CDMA receiver consists of 1040
correlators, each incorporating a form of
[Sigma][Delta]
modulation called recycling integrator to obtain a 9b quantized correlation
value between a received signal and a PN sequence. Fabricated in 0.35
um
double-metal double-poly CMOS, the chip occupies 22.8mm
2
and dissipates 23mW with a 1.8V supply.
21.5 An
Analog 0.25
um
BiCMOS Tailbiting MAP Decoder
10:45
AM
M.
Moerz
1,
2,
T. Gabara
1,
R. Yan
1,
J. Hagenauer
2
1Lucent
Technologies, Bell Labs, Murray Hill, NJ
2Munich
Univ. of Technology, Munich, Germany
A
fully-analog 0.25
um
BiCMOS tailbiting MAP decoder with 1/2 code rate has measured BER matching
simulated results over the full 0 to 7dB Eb/N
[omicron]
range. The measured transient impulse response indicates an operating rate of
320Mb/s while dissipating only 20mW. A digitally-equivalent circuit would
consume significantly more power, area, and delay.
21.6 A
550Mb/s GMR Read/Write Amplifier using 0.5
um
5V
CMOS Process
11:00
AM
S.
Lam, L. Cheng, D. Young
Marvell
Semiconductor, Inc., Sunnyvale, CA
An
8-channel CMOS GMR amplifier read path includes a 0.5nV/
[radical]Hz
noise level amplifier with -3dB bandwidth >300MHz. The 8V write driver has
<680ps rise/fall time (10%-90% with L
H=80nH
and I
WR=+/-35mA).
The chip includes thermal asperity, fault detection, servo bank write, pinned
layer reversal (PLR) and digital programmability for MR bias current, read
gain, write current, and write data input impedance.
CONCLUSION 11:15
AM