SESSION
WA 20
SALON
9,
Wed,
9
8:30
AM
OVERSAMPLING
CONVERTERS
Chair:
B. Brandt, National Semiconductor, Salem, NH
Associate
Chair: B-S. Song, Univ. of California, San Diego, CA
20.1 A
DC Measurement IC with 130nV
pp
Noise in 10Hz
8:30
AM
A.
Thomsen, E. de Angel, S. Wu, A. Amar, L. Wang, W. Lee
Cirrus
Logic Inc., Austin, TX
A
DC measurement IC consists of an instrumentation amplifier, a 4th-order
[Sigma][Delta]
modulator, a digital filter and a serial interface. The input amplifier uses
chopper stabilization and multipath feedforward compensation to achieve 130nV
pp
in 10Hz and <70nV/
deg.C
offset drift in 0.6
um
CMOS.
20.2 A
2.5MSample/s Multi-Bit
[Sigma][Delta]
CMOS ADC with
95dB
SNR
9:00
AM
Y.
Geerts, M. Steyaert, W. Sansen
Katholieke
Univ. Leuven, Heverlee, Belgium
A
multi-bit
[Sigma][Delta]
ADC converter in 0.65
um
CMOS employs speed-optimized data weighted averaging, resulting in 60MHz clock
and 2.5MSample/s output rate. The converter has 95dB SNR, 89dB SNDR and 97dB
dynamic range. It consumes 295mW at 5V and occupies 5.3mm
2.
20.3 A
90dB SNR, 2.5MHz Output Rate ADC
9:30
AM
I.
Fujimori, L. Longo
1,
A. Hairapetian
1,
K. Seiyama
2,
S. Kosic,
S.-l.
Chan
AKM
Semiconductor, San Diego, CA
1Newport
Communications, Irvine, CA
2Asahi-Kasei
Microsystems, Atsugi, Kanagawa, Japan
A
16b 2.5MHz output rate ADC achieves 90dB SNR and 102dB SFDR. A 2-1-1 cascaded
[Sigma][Delta]
modulator with 4b quantizers and bi-directional DWA makes all quantization
noise contributions negligible at 8x oversampling. The 24.8mm
2
chip in 0.5
um
CMOS including decimator and VREF, consumes 270mW at 5V.
BREAK 10:00
AM
20.4 A
10.7MHz IF-to-Baseband
[Sigma][Delta]
A/D Conversion System for AM/FM Radio Receivers
10:15
AM
E.
van der Zwan, K. Philips, C. Bastiaansen
Philips
Research Lab, Eindhoven, The Netherlands
[Sigma][Delta]
modulation with integrated quadrature mixing is used for A/D conversion of a
10.7MHz IF input signal. The baseband output signal has maximum
carrier-to-noise ratios of 92dB in 9kHz (AM) and 77dB in 200kHz (FM), and the
IM3 is >75dB. Including down conversion and decimation filtering, the A/D
converter occupies 2mm
2
in 0.35
um
digital CMOS.
20.5 A
Two-Path Bandpass
[Sigma][Delta]
Modulator with Extended Noise Shaping
10:45
AM
A.
Tabatabaei, K. Kaviani, B. Wooley
Stanford
Univ., Stanford, CA
A
2MHz 3-stage bandpass
[Sigma][Delta]
modulator uses 0.25
um
CMOS. Bandpass noise shaping in the third stage of the modulator achieves 75dB
dynamic range with 70dB maximum SNDR. The active area of the experimental
circuit is 2.8mm
2,
and it dissipates 140mW at 2.5V.
20.6 A
120dB Multibit SC Audio DAC with Second-Order Noise Shaping
11:15
AM
X-M.
Gong, E. Gaalaas
1,
M. Alexander, D. Hester, E. Walburger,
J.
Bian
2
Cirrus
Logic, Austin, TX
1Analog
Devices, Norwood, MA
2Standard
Microsystems, Austin, TX
A
multibit SC DAC employing second-order dynamic element matching (DEM) achieves
117dB SNR and -100dB total harmonic distortion over a 40kHz bandwidth. The
advanced DEM technique guarantees no noise floor modulation, and has a high
tolerance to element mismatch.
CONCLUSION 11:30
AM