SESSION
MP 2
SALON
1-6,
Mon.,
7
1:30
PM
NYQUIST-RATE
DATA CONVERTERS
Chair:
K. Poulton, Agilent Technologies, Palo Alto, CA
Associate
Chair: K. Martin, Univ. of Toronto, Toronto, Ontario,
Canada
2.1 A
14b 100MSample/s 3-Stage A/D Converter
1:30
PM
C.
Moreland, M. Elliott, F. Murden, J. Young, M. Hensley, R. Stop
Analog
Devices, Inc., Greensboro, NC
A
14b ADC uses a three-stage subranging architecture. Each conversion stage
consists of a string of serially-connected folding amplifiers which produce low
bit-error-rate gray-coded output data. A prototype converter in a 0.8
um
double-poly complementary bipolar process achieves a 100MSample/s conversion
rate with 1.25W dissipation.
2.2 A
13b 40MSample/s CMOS Pipelined Folding ADC with
Background
Offset Trimming
2:00
PM
M-J.
Choe, B.-S. Song
1,
K. Bacrania
2
Univ.
of Illinois, Urbana, IL
1Univ.
of California, San Diego, CA
2Intersil
Semiconductor, Melbourne, FL
Pipelining
and background offset trimming enhances performance of a CMOS
folding/interpolating ADC to a 13b level. The prototype, further refined using
subranging and digital correction, has 82dB SFDR. The chip occupies 8.7mm
2
in 0.5
um
CMOS and consumes 800mW at 5V.
2.3 A
12b 65MSample/s CMOS ADC with 81dB SFDR at
120MHz
2:30
PM
L.
Singer, S. Ho, M. Timko, D. Kelly
Analog
Devices, Inc., Wilmington, MA
A
pipeline ADC using digital calibration and bootstrapped input switches achieves
81dB SFDR for a 120MHz analog input. With a 2.5MHz analog input, SNR is 70dB
and SFDR is 85dB. The 10mm
2
ADC is realized in 0.5
um
double-poly CMOS and dissipates 515mW from a 5V analog / 3V digital supply.
BREAK 3:00
PM
2.4 A
3.3V 12b 50MSample/s A/D Converter in 0.6
um
CMOS
with 80dB SFDR
3:15
PM
H.
Pan, M. Segami, M. Choi, J. Cao, F. Hatori, A. Abidi
Univ.
of California, Los Angeles, CA
A
6b-7b two-stage pipelined ADC uses bootstrapping to linearize the sampling
switch of on-chip track-hold to achieve over 80dB SFDR for signal frequencies
up to 75MHz without trimming, calibration, or dithering. INL is 1.3LSB, DNL is
0.8LSB. In 0.6
um
CMOS, the active area is 16mm
2
and the ADC dissipates 850mW from 3.3V supply.
2.5 An
8b 80MSample/s Pipelined ADC with Background
Calibration
3:45
PM
J.
Ming, S. Lewis
Univ.
of California, Davis, CA
A
pipelined ADC uses adaptive background calibration to minimize the effects of
interstage gain errors. It achieves 0.33 LSB DNL, 0.49 LSB INL, and 46dB peak
SNDR. It dissipates 250mW from 3V and occupies 10.3mm
2
in single-poly 0.5
um
CMOS.
2.6 A
Self-Trimming 14b 100MSample/s CMOS DAC
4:15
PM
A.
Bugeja, B-S. Song
1
Texas
Instruments, Dallas TX
1University
of California, San Diego, CA
A
CMOS DAC uses self-trimming to achieve 14b INL/DNL and a track/attenuate output
sampler to reach 72dB SFDR at 42MHz output frequency. The chip occupies 11mm
2
in 0.35
um
CMOS and consumes 180mW at 3V at 100MSample/s.
2.7 A
14b 20MSample/s CMOS Pipelined ADC
4:45
PM
H-S.
Chen, K. Bacrania, B-S. Song
1
Intersil
Semiconductor, Melbourne FL
1University
of California, San Diego, CA
A
pipelined ADC uses capacitor-error averaging, look-ahead decision-making and
digital correction to achieve 14b DNL, 13b INL and 87.6dB SFDR at 20MSamples/s
with no trim or calibration. A prototype in 0.5
um
CMOS is 4.5x2.4mm
2
and consumes 720mW at 5V.
CONCLUSION 5:00
PM