SESSION
WA 18
SALON
7,
Wed,
9
8:30
AM
WIRELINE
COMMUNICATIONS
Chair:
L. Tan, Broadcom Corp., Irvine, CA
Associate
Chair: C. Chien, Rockwell Science Center,
Thousand
Oaks, CA
18.1 A
CMOS HDSL2 Analog Front-End
8:30
AM
A.
Gattani
1,
D. Cline, P. Hurst
2,
P. Mosinskis
3
Level
One Communications, Inc., Sacramento, CA
1Now
at Level One Communications, Inc., Morganville, NJ
2Univ.
of California, Davis, CA
3Now
at Aanetcom, Allentown, PA
A
5V 0.5
um
CMOS AFE IC for HDSL2 incorporates transmit DAC, noise shaping filters, output
buffer, receive AGC, and ADC. The 14.2mm
2
AFE consumes 525mW and provides 82dB SNDR in both transmit and receive paths.
It supports variable data rates from 63kb/s up to 2.32Mb/s, and supports
>14kft (26AWG) reach at 1.544Mb/s.
18.2 A
Broadband High-Voltage SLIC
for
a Splitterless and Transformerless
Combined
ADSL-Lite/POTS Linecard
9:00
AM
B.
Zojer, R. Koban, J. Pichler
Infineon
Technologies, Villach, Austria
A
B-SLIC combines full voiceband/ringing functions and enables ADSL-Lite data
transmission. THD is <-60dB for 25Vpp signals up to 550kHz. The 33mm
2
chip in a 170V smart power SLIC process enables a voice/data system without
analog filters, transformers or relays.
18.3 A
Gigabit Transceiver Chip Set for UTP CAT-6 Cables
in
Digital
CMOS
Technology
9:30
AM
K.
Azadet, M-L. Yu, P. Larsson, D. Inglis
Lucent
Technologies, Bell Labs, Holmdel, NJ
A
2.5V 0.25
um
digital CMOS transceiver chip set achieves 1Gb/s full-duplex transmission over
100m of unshielded twisted-pair (UTP) CAT-6 with >10
-9
BER using no error correction. The chip set dissipates 400mW (analog) and 500mW
(digital).
BREAK 10:00
AM
18.4 A
3V Low-Power 0.25
um
CMOS 100Mb/s Receiver for
Fast
Ethernet
10:15
AM
O.
Shoaei, A. Shoval, R. Leonowich
Lucent
Technologies, Bell Labs, Allentown, PA
A
125Mbaud receiver for 10/100 fast ethernet in 3V 0.25
um
digital CMOS achieves 140m reach. The analog receiver includes ACG with
baseline wander correction, equalizer and DC offset correction. The 0.984mm
2
receiver consumes 25mA from a single 3.3V power supply.
18.5 A
Mixed-Signal DFE/FFE Receiver for 100Base-TX
Applications
10:45
AM
P.
Kelly, D. Ray, D. Vogel
Level
One Communications, Sacramento, CA
A
mixed-signal receiver for 100Base-TX uses mixed-signal techniques for
decision-feedback and feed-forward equalization, baseline wander compensation,
and digital timing recovery. The receiver occupies 1mm
2
in 0.35
um
single-poly CMOS and dissipates 80mW at 3.3V.
18.6 A
CMOS 125MHz Fiber/TP Media Converter with Auto
Offset
Cancellation Post Amplifier and Pre-Emphasis
LED
Driver
11:15 AM
J-C.
Shieh, J. Cao, C-C. Shih
Allayer
Technologies Corp., San Jose, CA
A
125MHz 100Base-TX/100Base-FX media converter with integrated post-amplifier and
LED driver features a low-power all-digital data-driven clock recovery. The
temperature-compensated LED driver uses pre-emphasis to precisely control the
output optical waveform. This chip dissipates 0.68W on a 7mm
2
die using 0.5
um
CMOS.
18.7 A
Combined 10/125Mbaud Twisted-Pair Line Driver
with
Programmable Performance / Power Features
11:45
AM
A.
Shoval, O. Shoaei, R. Leonowich
Lucent
Technologies, Bell Labs, Allentown, PA
A
single-chip 0.65mm
2
3.3V 0.25
um
CMOS 10/125Mbaud twisted-pair driver dissipates 151mW in 100Base-TX mode and
255mW in 10Base-T mode. The driver includes amplitude feedback and can be
programmmed to optimize power dissipation for different performance levels.
CONCLUSION 12:00
NOON