SESSION
WA 17
SALON
1-6,
Wed,
9
8:30
AM
LOGIC
AND SYSTEMS
Chair:
W. Athas, Information Sciences Institute,
Marina
Del Rey, CA
Associate
Chair: V. Oklobdzija, Integration Corp., Berkeley, CA
17.1 A
2nd Generation 440ps SOI 64b Adder
8:30
AM
D.
Stasiak, J. Tran, F. Mounes-Toussi, S. Storino
IBM
Corp., Rochester, MN
A
64b adder in SOI technology and techniques to maintain performance are
described. First-generation SOI achieves up to 28% performance gain over bulk
CMOS, and 2nd SOI generation delivers an additional 21%. In a 660MHz processor,
the adder accounts for floating body effects in SOI devices which cause history
effects, bipolar currents, and lower noise margins on dynamic circuits.
17.2 Conditional
Capture Flip-Flop Technique for
Statistical
Power Reduction
9:00
AM
B-S.
Kong, S-S. Kim, Y-H. Jun
Hyundai
Microelectronics, Seoul, Korea
Conditional-capture
flip-flop statistically minimizes power consumption saving 20-67% power for
input switching activity
<=0.5,
with no degradation or latency. The flip-flops have soft clock edge for
time-borrowing and clock-skew immunity. This flip-flop in an 8b counter saves
51% power compared to that of a conventional counter, leading to 30% overall
power reduction.
17.3 Asynchronous
Interlocked Pipelined CMOS Circuits Operating at 3.3-4.5MHz
9:30
AM
S.
Schuster, W. Reohr, P. Cook, D. Heidel, M. Immediato, K. Jenkins
IBM
Research Center, Yorktown Heights, NY
An
asynchronous circuit technique suitable for multi-GHz operation uses
interlocked local clocks. These circuits drive a path through a typical 64b
multiplier stage at 3.3-4.5GHz in 0.18
um
1.5V CMOS technology.
BREAK 10:00
AM
17.4 A
Dynamic Voltage-Scaled Microprocessor System
10:15
AM
T.
Burd, T. Pering, A. Stratakos
1,
R. Brodersen
Univ.
of California, Berkeley, CA
1Volterra,
Freemont, CA
A
microprocessor in 0.6
um
3-metal CMOS consists of a dc-dc switching regulator, an ARM V4 microprocessor
with 16kB cache, a bank of 64kB SRAM ICs, and an interface IC. The supply
voltage and clock frequency can be dynamically varied from 1.2-3.8V in <70
us,
providing a range of 6-85 MIPs performance with an energy efficiency of
0.54-5.6mW/MIP.
17.5 Clock-Powered
CMOS VLSI Graphics Processor for Embedded Display Controller Application
10:45
AM
W.
Athas, N. Tzartzanis, W. Mao
1,
R. Lal, K. Chong, L. Peterson
2,
M.
Bolotski
3
Information
Sciences Institute, Marina del Rey, CA
1Synopsys
Corp., Mountain View, CA
2Chalmers
Univ. of Technology, Goteborg, Sweden
3MicroDisplay,
Corp., San Pablo, CA
A
2mW, 14.5MHz CMOS VLSI graphics processor uses clock-powered logic to reduce
power dissipation. The chip is in 0.5
um
bulk CMOS optimized for 3.3V supply. The graphics processor uses a 1.7V supply
for dc-powered static CMOS and a resonant clock generator for clock-powered
signals.
17.6 A
Variable-Frequency Parallel I/O Interface with Adaptive Power Supply Regulation
11:15
AM
G-Y.
Wei, J. Kim, D. Liu, S. Sidiropoulos
1,
M. Horowitz
1
Stanford
Univ., Stanford, CA
1also
with Rambus Inc., Mountain View, CA
Adaptive
power supply regulation applied to an I/O interface maximizes energy
efficiency. Both transmitter and receiver operate from a variable supply set by
the operating frequency and delay line of a dual loop delay-locked loop, and
regulated by a digitally-controlled switching power supply. A prototype in 0.35
um
CMOS has I/O operating from 0.2-1.0Gb/s over 1.2-3.2V regulated supply range.
CONCLUSION 11:45
AM