SESSION
TP 16
SALON
10-15,
Tues,
8
1:30
PM
NON-VOLATILE
AND SRAM
Chair:
G. Smarandoiu, Atmel Corp., San Jose, CA
Associate
Chair: J. Miyamoto, Toshiba Corp., Sakae-ku,
Yokohama,
Japan
16.1 A
16Mb 400MHz Loadless CMOS 4-Transistor
SRAM
Macro
1:30
PM
K.
Takeda, Y. Aimoto, N. Nakamura, H. Toyoshima, T. Iwasaki
1,
K.
Noda, H. Matsui, S. Itoh, S. Masuoka, T. Horiuchi, A. Nakagawa,
K.
Shimogawa, H. Takahashi
NEC
Corp, Sagamihara, Japan
1NEC
Informatec Systems, Ltd.
A
16Mb 400MHz loadless CMOS 4-transistor SRAM macro has: end-point dual-pulse
driver for stable data hold and minimum cycle time, wordline voltage-level
comparison for stable static data hold, and all-adjoining twisted bitline to
reduce bitline coupling capacitance.
16.2 An
833MHz 1.5W 18Mb CMOS SRAM with 1.67Gb/s/pin
2:00
PM
H.
Pilo, A. Allen, J. Covino, P. Hansen, S. Lamphier, C. Murphy,
T.
Traver, P. Yee
IBM
Microelectronics, Essex Junction, VT
An
833MHz 18Mb CMOS SRAM with 1.67Gb/s/pin data rate uses 0.18
um
CMOS process with copper interconnects. The SRAM operates in double-data-rate
mode and consumes 1.5W at 833MHz. A data-to-echo-clock tracking system,
combined with data-symetric output drivers, delivers maximum data windows
across the SRAM frequency stage.
16.3 The
Future of Ferroelectric Memories
2:30
PM
C.
Paz de Araujo, L. McMillan, V. Joshi, N. Solayappan, M. Lim,
K.
Arita
1,
N. Moriwaki
1,
H. Hirano
1,
T. Baba
2,
Y. Shimada
1,
T. Sumi
1,
E.
Fujii
1,
T. Otsuki
1
Symetrix
Corp., Colorado Springs, CO
1Matsushita
Corp., Osaka, Japan
2Panasonic
Technologies, Inc., Cupertino, CA
Low
and medium density FeRAM promise 1V operation, 1-10ns write, and non-volatility
with virtually no endurance limit. FeRAM technology covered focuses on FeRAM
device physics, reliability and device trends for 0.25 to 0.18
um
and beyond. Embedded FeRAM technology is compatible with evolving CMOS
technology. Capacitor scaling to 0.04
um2
is possible.
BREAK 3:00
PM
16.4 A
128kb FeRAM Macro for a Contact/Contactless Smart-Card Microcontroller
3:15 PM
J.
Yamada, T. Miwa, H. Koike, H. Toyoshima, K. Amanuma,
S.
Kobayashi, T. Tatsumi. Y. Maejima, H. Hada, H. Mori,
S.
Takahashi, H. Takeuchi, T. Kunio
NEC
Corp., Sagamihara, Japan
A
FeRAM for contact/contactless smart-card controller, using 0.35
um
3-metal CMOS and CMVP, has memory size from 32kb to 128kb, 0.3mA current
consumption, and >10
8
read/write cycle endurance with supply from 2.7 to 5.5V.
16.5 A
0.4
um3.3V
1T1C 4Mb Nonvolatile Ferroelectric RAM with Fixed Bitline Voltage Reference and
Data Protection Circuit
3:45 PM
B-G
Jeon, M-K. Choi, Y. Song, S-K. Oh, Y. Chung, K-D. Suh, K. Kim
Samsung
Electronics Co., Yongin, Korea
A
0.4
um
3.3V 1T1C 4Mb nonvolatile ferroelectric RAM uses charge evaluation with stable
voltage generator free from fatigue and endurance to provide optimum reference
for all cells, data protection to eliminate loss during power-off, and test
circuit for optimum read-pulse width.
16.6 A
40mm
2
3V 50MHz 64Mb 4-Level Cell NOR Type
Flash
Memory
4:15 PM
G.
Campardo, R. Micheloni, S. Commodaro, E. Yero, M. Zammattio, S. Mognoni, A.
Sacco, M. Picca, A. Manstretta, M. Scotti, I. Motta,
C.
Golla, A. Pierin, A. Ohba
1,
T. Futatsuya
1,
R. Makabe
1,
S. Kawai
1,
Y.
Kai
1,
N. Ajika
1,
S. Shimizu
1,
T. Ohnakado
1,
T. Sugihara
1,
R. Bez,
A.
Grossi, A. Modelli, O. Khouri
2,
G. Torelli
2
STMicroelectronics,
Agrate Brianza, Italy
1Mitsubishi
Electric Corp., Itami, Japan
2University
of Pavia, Pavia, Italy
A
3V-only 64Mb 4-level-cell (2b/cell) Nor Flash memory uses 0.18
um
CMOS. The 40mm
2
device is organized in 64 1Mb sectors. Hierarchical column and row decoding
ensures complete isolation between sectors during any operation.
130ns-access-time synchronous and 50MHz-data-rate burst mode readout are
provided.
16.7 A
Channel-Erasing 1.8V-Only 32Mb NOR Flash EEPROM with a Bit-Line Direct-Sensing
Scheme
4:45 PM
S.
Atsumi, A. Umezawa, T. Tanzawa, T. Taura, H. Shiga, Y. Takano, T. Miyaba, M.
Matsui, H. Watanabe, K. Isobe, S. Kitamura,
S.
Yamada, M. Saito, S. Mori, T. Watanabe
Toshiba
Microelectronics Corp., Sakae-ku, Yokohama, Japan
A
1.8V-only 32Mb NOR flash EEPROM with channel-erasing realizes a 0.49
um2
cell in 0.25
um
CMOS. A block decoder circuit with erase-reset sequence is used for
channel-erasing. At 1.8V, 90ns access time is obtained by bit-line
direct-sensing, word-line-boosted voltage pooling, and erased threshold
compaction.
CONCLUSION 5:15
PM