SESSION
TP 15
SALON
9,
Tues,
8
1:30
PM
HIGH-SPEED
I / O
Chair:
M. Leary, ATI Research, Inc., Santa Clara, CA
Associate
Chair: W. Bowhill, Compaq Computer Corp.,
Shrewsbury,
MA
15.1 Dynamic
Termination Output Driver
for
a 600MHz Microprocessor
1:30
PM
S.
Vishwanthaiah, M. Ang, J. Starr
1,
A. Taylor
Sun
Microsystems, Inc., Palo Alto, CA
1Cisco
Systems, Inc., San Jose, CA
Output
driver circuits have output impedence control, linearization, and slew-rate
control, for 1.5V operation in 0.18
um
CMOS. The signaling scheme uses dynamically-configured termination circuits.
15.2 Embedded
Low-Cost 1.2Gb/s Inter-IC Serial Data Link in 0.35
um
CMOS
2:00
PM
G.
den Besten
Philips
Research Labs, Eindhoven, The Netherlands
A
low-cost inter-IC serial data link for high data rates includes both bit and
word synchronization using an encoding scheme. Low-swing differential signaling
enables low-EMI and low-power. 1.2Gb/s is demonstrated in 0.35
um
CMOS. Circuit area is 0.12mm
2.
Power consumption is 60mW. BER is <10
-14.
15.3 A
90mW 4Gb/s Equalized I/O Circuit with
Input
Offset Cancellation
2:30
PM
M-J.
Lee, W. Dally, P. Chiang
Stanford
Univ. Stanford, CA
A
serial link circuit operates at 4Gb/s over 10m of 24AWG cables consuming 90mW.
Measured jitter with quiet supply is 16.4ps p-p and measured supply sensitivity
of jitter is 0.08ps/mV p-p. The test chip in 0.25
um
CMOS with 2.5V nominal supply occupies <0.1mm
2
active area.
BREAK 3:00
PM
15.4 A
1.25Gb/s CMOS Receiver Core with
Plesiochronous
Clocking Capability for
Asynchronous
Burst Data Acquisition
3:15
PM
T.
Yoshikawa, T. Yoshida, T. Ebuchi, H. Yamauchi
Matsushita
Electric Industrial Co., Ltd., Osaka, Japan
A
technique for timing clock generation and data acquisition from Gb/s
asynchronous burst data achieves 1.25Gb/s data-rate and 10
-13
order BER with 30mW/Port dissiipation and fast phase and frequency lock
capability using plesiochronous clock.
15.5 A
2.4Gb/s/pin Simultaneous Bidirectional Parallel Link with Per-Pin Skew
Compensation
3:45
PM
E.
Yeung, M. Horowitz
Stanford
Univ., Stanford, CA
An
8b wide single-ended simultaneous bidirectional transceiver test chip in 0.4
um
CMOS permits study of the major challenges in high-performance, low-cost
parallel-link design. Each pin contains on-chip voltage samplers to measure
link internal voltage margins, and per pin timing adjustment to compensate for
inter-bit skew and to measure timing margins.
15.6 A
Scalable 32Gb/s Parallel Data Transceiver with
On-Chip
Timing Calibration Circuits
4:15
PM
K.
Yang, T. Lin, Y. Ke
HotRail,
Inc., San Jose, CA
A
parallel data transceiver provides point-to-point interconnect between chips.
Data transfer rate per differential pair is 1.6Gb/s. An on-chip timing
calibration circuit performs data de-skewing and timing optimization. The macro
consumes <400mW with <8ns latency and <10
-15
BER. In 0.25
um
CMOS and measures 2500x700
um2
using BGA or QFP packages. Built-in self test (BIST) logic is implemented for
product testing.
15.7 A
20Gb/s CMOS Multi-Channel Transmitter and Receiver Chip Set for
Ultra-High-Resolution
Digital
Display
4:45
PM
M.
Fukaishi, K. Nakamura, H. Heiuchi, Y. Hirota, Y. Nakazawa,
H.
Ikeno, H. Hayama, M. Yotsuyanagi
NEC
Corp., Sagamihara, Japan
A
multi-channel TX and RX chip set operating four channels at 20Gb/s and using 0.25
um
CMOS compensates for phase differences between multiple chips and frequency
differences between TX and RX chips. The chip has a self-alignment phase
detector with parallel output for a high-speed clock and data recovery circuit,
and a fully-pipelined 8B10B encoder.
CONCLUSION 5:15
PM