SESSION
TP 14
SALON
8,
Tues,
8
1:30
PM
SIGNAL
PROCESSING FOR MULTIMEDIA
Chair:
S. Molloy, Luxxon Corp., San Jose, CA
Associate
Chair: T. Yamazaki, Sony Electronics, San Jose, CA
14.1 A
60MHz 240mW MPEG-4 Video-Phone LSI with
16Mb
Embedded DRAM
1:30 PM
T.
Nishikawa, M. Takahashi, M. Hamada, T. Takayanagi, H. Arakida, N. Machida, H.
Yamamoto, T. Fujiyoshi, Y. Matsumoto, O. Yamagishi, T. Samata, A. Asano, T.
Terazawa
1,
K. Ohmori
1,
J. Shirakura
1,
Y.
Watanabe
1,
H. Nakamura
2,
S. Minami, T. Kuroda, T. Furuyama
Toshiba
Corp., Kawasaki, Japan
1Toshiba
Microelectronics Corp., Kawasaki, Japan
2Toshiba
Information Systems Corp., Kawasaki, Japan
A
single-chip MPEG-4 video-phone system LSI in a 0.25
um
CMOS, quad-metal technology with 16Mb embedded DRAM integrates three 16b RISC
processors and consumes 240mW at 60MHz. Optimization of the embedded DRAM
configurations and architectural efforts reduce power dissipation by 78%
compared to that of a conventional design.
14.2 A
30Frames/s Megapixel Real-Time
CMOS
Image Processor
2:00 PM
D.
Doswald, B. Schreier, S. Oetiker, J. Häfliger, P. Blessing,
N.
Felber, W. Fichtner
ETH,
Zurich, Switzerland
A
30frames/s 1024x1024 pixel real-time 0.35
um
CMOS image processor ASIC corrects black current and white imbalance pixelwise,
interpolates images from a 1-CCD camera head over nine lines and performs a
color space transformation for true-color motion images.
14.3 A
Parallel Vector Quantization Processor Eliminating Redundant Calculations for
Real-Time Motion Picture Compression
2:30 PM
T.
Nozawa, M. Konda, M. Fujibayashi, M. Imai, T. Ohmi
1
EE
Dept., Tohoku Univ., Aobaku, Sendai, Japan
1New
Industry Creation Hatchery Ctr., Tohoku Univ.
A
parallel vector quantization processor eliminating redundant calculation
handles 2048 template vectors (16-elements/12b) by a single chip and is
applicable to real-time compression of 30frames/s full-color VGA images. A
real-time motion picture compression system employs this chip.
BREAK 3:00
PM
14.4 A
200MHz 0.25W Packet Audio Terminal Processor for Voice-over-Internet Protocol
Applications
3:15 PM
B.
Martin, I. Buckley, P. Bednarz, D. Chrissan, K. Amiri, C. Burnett,
C.
Eddington, W. Lin, G. Maturi, H. Subagio, G. Teng, J. Waite,
Y.-T.
Yong
8x8,
Inc., Santa Clara, CA
Voice-over-IP
(VoIP) terminals used in phone terminal applications require a low-power
implementation suitable for the limited chassis area of these devices. This
200MHz VoIP terminal processor in 0.18
um
CMOS implements a complete IP phone solution from audio samples to compressed
TCP/IP packetized network signals with 2Mb of on-chip RAM.
14.5 A
720
uW
50MOPS 1V DSP for a Hearing Aid Chip Set
3:45
PM
P.
Mosch, G. van Oerle
1,
S. Menzl
1,
N. Rougnon-Glasson,
K.
Van Nieuwenhove
2,
M. Wezelenburg
2
Xemics
SA, Neuchâtel, Switzerland
1Phonak
AG, Stäffa, Switzerland
2Frontier
Design, Leuven, Belgium
The
flow and techniques are used to design a digital signal processor chip
containing 1.3M transistors and operating at 2.5MHz for hearing-aid
applications. Its DSP consumes 720mW at 1.2V supply in 0.25
um
CMOS, and performs 50M 22b OPS. The DSP achieves 0.015mW/MOPS performance, a
factor 6 better than prior results.
14.6 A
4-Way VLIW Embedded Multimedia Processor
4:15
PM
A.
Suga, T. Sukemura, H. Takahashi, K. Wada, H. Miyake,
Y.
Nakamura, Y. Takebe, K. Azegami, Y. Hirose, M. Kimura,
H.
Okano, T. Shiota, M. Saito, S. Wakayama, T. Ozawa, T. Satoh
1,
A.
Sakurai
1,
T. Katayama
1,
K. Abe, K. Kuwano
2
Fujitsu
Labs Ltd., Nakahara-ku, Kawasaki, Japan /
1Fujitsu
Ltd.
2Fujitsu
LSI Technology Ltd.
A
350MHz 5.6GOPS 1.4GFLOPS 4-way VLIW embedded multimedia microprocessor occupies
7.5x7.5mm
2
die in 0.18
um
1.8V five-layer-metal CMOS. VLIW, SIMD, 3-valued predicate mechanism, dual-load
operation and dual-fetch contribute to performance.
14.7 A
7.1GB/s Low-Power 3D Rendering Engine in 2D Array Embedded Memory Logic CMOS
4:45 PM
Y.-H.
Park, S.-H. Han, J.-S. Kim, S.-J. Lee, J.-H. Kook, J.-W. Lim,
R.
Woo, H.-J. Yoo, Je.-H. Lee
1,
Ja.-H. Lee
1
Korea
Advanced Inst. of Science and Technology, Taejon, Korea
1Hyundai
Electronics Ind. Co., Ltd., Kyoungki-do, Korea
A
52mm
23D
rendering engine with 7.1GB/s bandwidth and 11.1M polygon/s drawing speed uses
0.35
um
embedded memory logic technology and 2D array architecture. Main features of
embedded frame buffer are partial word line activation and sequential block
activation to reduce power consumption of nodal memory to <20mW.
14.8 Heterogeneous
Multi-Processor for Composition and Enhancement of Video
5:00 PM
M.
Strik, A. Timmer, J. van Meerbergen, E. Waterlander, F. Harmsze, A. Vaasen, L.
Sevat, M. Oosterhuis, G. J. van Rootselaar,
H.
van Herten, E. Jaspers, J. Janssen, G. Essink
Philips
Research Labs, Eindhoven, The Netherlands
A
system implements a set of video applications on a single die for TV display
processing requiring up to 10 GOPS. Multiple data-driven processors work in
parallel and communicate on-chip. Real time video processing is performed on a
maximum of 10 video streams in parallel.
CONCLUSION 5:15
PM