SESSION
TP 13
SALON
7,
Tues,
8
1:30
PM
TECHNOLOGY
DIRECTIONS: LOW-TEMPERATURE CIRCUITS AND DIAGNOSTIC TECHNIQUES FOR
MICROPROCESSORS
Chair:
B. Bidermann, S3 Incorporated, Santa Clara, CA
Associate
Chair: T. Tredwell, Eastman Kodak Co.,
Rochester,
NY
13.1 CMOS
Circuit Technology for
Sub-Ambient
Temperature Operation
1:30
PM
I.
Aller, K. Bernstein
1,
U. Ghoshal
2,
H. Schettler, S. Schuster
3,
Y.
Taur
3,
O. Torreiter
IBM
Entwicklung GmbH, Boeblingen, Germany
1IBM
Microelectronics, Essex Jct., VT
2IBM
Research, Austin Research Lab, Austin, TX
3IBM
Research, T. J. Watson Research Ctr., Yorktown Heights, NY
Sub-ambient
temperature operation can remove important scaling and performance bottlenecks
in 100nm bulk and SOI CMOS technologies. The design and performance of logic
circuits, memory circuits, and the back-end interconnection circuits, for
sub-ambient temperature server applications are described.
13.2 Refrigeration
Technologies for Sub-Ambient
Temperature
Operation of Computing Systems
2:00
PM
U.
Ghoshal, R. Schmidt
1
IBM
Research, Austin Research Lab, Austin, TX
1IBM
Server Div., Poughkeepsie, NY
Sub-ambient
temperature operation can significantly increase the performance and
reliability of computing systems. The advantages and limitations of two
important refrigeration technologies - mechanical vapor compression
refrigeration and thermoelectric coolers - for server applications are described.
13.3 Threshold
Cancelling Logic (TCL): A Post-CMOS Logic Family Scalable Down to 0.02
um
2:30
PM
I.
Kohno, T. Sano
1,
N. Katoh, K. Yano
Hitachi
Central Research Lab, Tokyo, Japan
TCL
maintains speed advantages at constant sub-threshold leakage over conventional
CMOS down to 0.02
um,
by using reduced signal swing, separation of nMOS and pMOS gates, and a scaling
rule. Improved speed at low temperatures is experimentally confirmed.
BREAK 3:00
PM
13.4 Optical
Probing of Flip-Chip-Packaged
Microprocessors
3:15 PM
T.
Eiles, G. Woods, V. Rao
Intel
Corp., Santa Clara, CA
Optical
probing for circuit analysis of microprocessors uses a pulsed infrared laser
focused on the device diffusion, where an electro-optic effect in the depletion
region modulates the phase of the reflected light. The reflected light is
detected to reconstruct the electrical waveform. Waveforms with sub-50ps timing
accuracy and high acquisition speed are collected from processors in 0.18
um
technology.
13.5 Non-Invasive
Timing Analysis of G6
Microprocessor
L1 Cache using Backside
Time-Resolved
Photoluminescence
3:45 PM
S.
Polonsky, D. Knebel, P. Sanda, M. McManus, W. Huott
1,
A.
Pelella
1,
D. Manzer, S. Steen, S. Wilson
1,
Y. Chan
1
IBM
T.J. Watson Research Ctr., Yorktown Heights, NY
1IBM
S/390 Div., Poughkeepsie, NY
The
non-invasive backside IC characterization technique, picosecond imaging circuit
analysis (PICA), is applied to identification and analysis of a
cycle-time-limiting condition which occurred in an early pass of the S/390 G60
microprocessor cache. This analysis is fed back to hardware simulation for
model tuning and contributes to timely implementation of the S/390 G6 system,
and enhanced understanding of manufacturing device models.
13.6 Reduced
Substrate Noise Digital Design for
Improving
Embedded Analog Performance
4:15 PM
M.
Nagata, K. Hijikata, J. Nagai, T. Morie, A. Iwata
Hiroshima
Univ., Higashi-Hiroshima, Japan
Reduced
supply bounce CMOS suppresses substrate noise amplitude to
<=33%
of conventional CMOS, by optimizing recharge time constant of local charge
reservoirs for fast logic transistions. Substrate noise is measured with 100ps,
100
uV
resolution by a latch comparator with a gain-calibrated front-end level shifter
having 2GHz BW.
13.7 Accurate
In-situ Measurement of Peak Noise and Signal Delay Induced by Interconnect
Coupling
4:45 PM
T.
Sato, D. Sylvester, Y. Cao, C. Hu
Univ.
of California, Berkeley, CA
A
test chip demonstrates efficacy of an accurate in-situ noise and delay
measurement technique. Intended for generating circuit design guidelines and
verifying CAD models and tools, the technique experimentally characterizes the
noise peak height and the timing slew due to noise. Measured 400mV-peak
1ns-wide pulses are accurate to <40 mV.
CONCLUSION
5:15 PM