SESSION
TP 12
SALON
1-6,
Tues,
8
1:30
PM
FREQUENCY
SYNTHESIZERS AND DIVIDERS
Chair:
P. Davis, Bell Labs, Lucent Technologies, Reading, PA
Associate
Chair: G. Nasserbahkt, Proxim, Inc., Sunnyvale, CA
12.1 A
1.8V 3mW 16.8GHz Frequency Divider in
0.25um
CMOS
1:30 PM
H.
Wang
Bell
Labs, Lucent Technologies, Murray Hill, NJ
A
static 1/2 frequency divider in standard 0.25
um
digtal CMOS operates above 16.8GHz with a 1.8V supply consuming ~3mW. The
circuit topology results in 3x speed improvement over prior art using the same
voltage and technology.
12.2 A
1.1GHz CMOS Fractional-N Frequency Synthesizer with a 3b 3rd-Order
[Sigma][Delta]
Modulator
1:45 PM
W.
Rhee, A. Ali, B-S. Song
1
Conexant
Systems, Newport Beach, CA
1Univ.
of California, San Diego, CA
A
1.1GHz fractional-N frequency synthesizer implemented in 0.5
um
CMOS uses a 3b 3rd-order
[Sigma][Delta]
modulator that exhibits less sensitivity to phase detector nonlinearity.
Synthesizing 900MHz with 1Hz resolution, it exhibits an in-band phase noise of
-92dBc/Hz at 10kHz offset with <-95dBc spur. The 11mm
2
chip dissipates 11mA from 2.5V.
12.3 An
Integrated 2.5GHz
[Sigma][Delta]
Frequency Synthesizer with 5
us
Settling and 2Mb/s Closed-Loop Modulation
2:00PM
S.
Willingham
1,
M. Perrott
1,
B. Setterberg, A. Grzegorek,
B.
McFarland
2
Agilent
Technologies, Palo Alto, CA
1Now
with Silicon Labs, Austin, TX
2Now
with T-Span Systems, Palo Alto, CA
A
2.5GHz CMOS
[Sigma][Delta]
fractional-N frequency synthesizer integrated on a baseband transceiver
includes 50Hz carrier resolution and closed-loop digital frequency modulation
at 1 and 2Mb/s. Settling time is
<=5us
and dissipation is 41mA at 3.3V
12.4 A
900MHz Local Oscillator using a DLL-Based
Frequency
Multiplier Technique for PCS Applications
2:30
PM
G.
Chien, P. Gray
Univ.
of California, Berkeley, CA
A
fully-integrated CMOS local oscillator utilizing a DLL-based frequency
multiplier to synthesize a 900MHz carrier with low close-in phase noise in
standard 0.35
um
CMOS achieves -123dBc/Hz phase noise at 60kHz offset while dissipating 130mW
from a 3.3V supply, meeting the requirements of the IS-137 dual-mode standard.
BREAK 3:00
PM
12.5 A
1.6GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL
Architecture
3:15
PM
L.
Lin, L. Tee, P. Gray
Univ.
of California, Berkeley, CA
A
fully-differential fully-integrated CMOS RF frequency synthesizer utilizing a
wideband PLL in standard 0.35
um
CMOS achieves -118dBc/Hz phase noise at 100kHz offset. It has -56dBc spurious
tone at 86.4MHz dissipating 84mW from 3.3V. 32dB effective PSRR is achieved
from 200kHz - 10MHz.
12.6 53GHz
Static Frequency Divider in a SiGe
Bipolar
Technology
3:45
PM
M.
Wurzer
1,
2,
T. Meister
1,
H. Knapp
1,
2,
K. Aufinger
1,
R. Schreiter
1,
S.
Boguth
1,
L. Treitinger
1
1Infineon
Technologies, Munich, Germany
2Technische
Univ., Wien, Austria
A
static frequency divider in 0.5
um/80GHz
f
T
SiGe bipolar technology operates up to 53GHz. The divider draws 122mA from 6.3V.
12.7 A
79GHz Dynamic Frequency Divider in SiGe
Bipolar
Technology
4:00
PM
H.
Knapp, T. Meister, M. Wurzer, D. Zöschg, K. Aufinger, L. Treitinger
Infineon
Technologies, Munich, Germany
A
dynamic frequency divider using regenerative frequency division operates up to
79GHz, close to the 80GHz f
T
of the SiGe bipolar technology. It draws 143mA from a 7.5V supply.
12.8 82GHz
Dynamic Frequency Divider in 5.5ps ECL
SiGe
HBTs
4:15
PM
K.
Washio, E. Ohue, K. Oda, R. Hayami, M. Tanabe
1,
H. Shinamoto
1,
T. Harad
2,
M. Kondo
Central
Research Lab, Hitachi, Ltd., Kokubunji, Tokyo, Japan
1Hitachi
Device Engineering, Co. Ltd., Musashino, Japan
2Device
Development Ctr., Hitachi, Ltd, Tokyo, Japan
Dynamic
and static frequency dividers operating up to 82GHz and 60GHz and dissipating
396 and 689mW respectively use 0.2
um
self-aligned 122GHz f
T
SiGe HBTs.
CONCLUSION 4:30
PM