SESSION
TA 10
SALON
9,
Tues,
8
8:30
AM
CLOCK
GENERATION AND DISTRIBUTION
Chair:
J. Maneatis, JGM Enterprises, Redwood City, CA
Associate
Chair: K. Donnelly, Rambus, Inc., Mountain View, CA
10.1 A
1.3 Cycle Lock-In Time Non-PLL/DLL Jitter
Suppression
Clock Multiplier Based on Direct
Clock
Cycle Interpolation for "Clock on Demand."
8:30
AM
T.
Saeki, M. Mitsuishi, H. Iwaki, M. Tagishi
NEC
Corp., Kawasaki, Kanagawa, Japan
A
1.3 cycle lock-in time non-PLL/DLL clock multiplier is based on direct clock
cycle interpolation with an array structure of
short-circuit-current-suppression interpolators. The circuits used in 622MHz
clock and data recovery achieve 40ps peak-to-peak jitter and satisfy the ITU-T
G.958 jitter tolerance specification.
10.2 A
Digitally-Controlled PLL with Fast Locking Scheme for Clock Synthesis Application
9:00
AM
I-C.
Hwang, S-W. Kim
Korea
Univ., Sungbuk-gu, Seoul, Korea
A
digitally-controlled phase-locked loop (DCPLL) in 3.3V 0.6
um
triple-metal CMOS achieves fast acquisition employing digital frequency
difference detector (DFDD). The prototype DCPLL provides 136ps peak-to-peak
cycle-to-cycle jitter at 400MHz (VCO at 800MHz). The acquisition time is
measured as 16 cycles (640ns) using the 25MHz reference.
10.3 An
Eight Channel 36GSample/s CMOS Logic Analyzer
9:30
AM
D.
Weinlader, R. Ho, C-K. Yang
1,
M. Horowitz
Stanford
Univ., Stanford, CA
1Univ.
of California, Los Angeles, CA
A
timing analyzer in 0.25
um
CMOS uses an oversampling input channel. On-chip compensation corrects both
static phase errors in the sampling clocks and sampler input referred offsets.
The analyzer achieves 27.8ps resolution with 0.39ps/mV noise sensitivity. A
technique for minimizing timing uncertainty due to cycle-to-cycle clock jitter
is presented.
BREAK 10:00
AM
10.4 On-Chip
Inductance Modeling of VLSI Interconnects
10:15
AM
X.
Qi, B. Kleveland, Z. Yu, S. Wong, R. Dutton, T. Young
1
Stanford
Univ., Stanford, CA
1Synopsys
Corp., Mountain View, CA
Modeling
of on-chip inductance captures 3D geometry and process technology effects.
Analytical formulae suitable for design are used to estimate inductance of test
structures. S-parameter characterization to 10GHz agrees with simulations and
analytical modeling. Consideration of substrate effects results in an 18%
reduction of wire inductance for wire spacing >40
um.
10.5 Active
GHz Clock Network using Distributed PLLs
10:45
AM
V.
Gutnik, A. Chandrakasan
Massachusetts
Institute of Technology, Cambridge, MA
A
distributed clock network alleviates problems of skew and jitter in
GHz-clock-speed microprocessors. A chip with a 4x4 array of PLLs in standard 0.35
um
single-poly CMOS achieves lock at 1.3GHz. The VCO, phase detector, and loop
filter have small-signal stability despite stringent large-signal (initial
locking) constraints. The PLLs each take <4000
um2
and consume 25mW at 3V.
10.6 Clock
Generation and Distribution for a
IA-64
Microprocessor
11:15
AM
S.
Rusu, S. Tam
Intel
Corp., Santa Clara, CA
The
clock generation and distribution for the first IA-64 microprocessor achieves
low skew over a large die using distributed programmable deskew units. Local
skew control compensates for load mismatches and within-die process variations,
as well as temperature and voltage gradients, with 12.5ps resolution. Debug
features include on-die clock shrink and control over deskew settings.
CONCLUSION 11:45
AM