ISSCC 1999 - TECHNOLOGY DIRECTIONS

• Summary
• Daytime Paper Sessions

Subcommittee Chair: Timothy Tredwell, Eastman Kodak, Rochester, NY.

HIGHLIGHTS

• SiGe, deep-submicron CMOS, and micromachining drive advances in RF communications circuits:
  
  • SiGe becoming mature for high-performance RF [4.1, 4.2]
    
  • Submicron and deep-submicron CMOS continues advance into 5 to13GHz RF building blocks [4.3, 4.4]
    
  • Micro-machining opening new opportunities for IF filters for silicon transceivers [4.7, 4.8]
• Low-power systems-on-a-chip enable portable OCR, vision, spectrophotometry, and display [12.1, 12.2, 12.3, 12.5]

• Human-implantable neural stimulation ICs with wireless power and data transmission using an RF link [12.6]

• Reconfigurable processors allow significant performance improvements over standard microprocessors and programmable DSPs [21.2, 21.3]

• ESD protection can be achieved in deep-submicron CMOS microprocessors [21.4]

• SOI comes of age:
  
  • Demonstration in a multi-million-transistor microprocessor that yield for SOI is equivalent to that of bulk CMOS [25.1]
    
  • New circuit techniques required for effective use of SOI-specific characteristics [25.1, 25.3, 25.6, 25.7]
    
  • Low-power SOI digital circuits for portable applications [25.2]
    
  • High-performance PowerPC 603, PowerPC 750, an advanced 64-bit PowerPC, and ALPHA SOI microprocessors [25.3, 25.4, 25.7]
    
  • Low-power SOI DRAM [25.5]

MOST-SIGNIFICANT RESULTS

• DECT transceiver chip set with integrated power amplifier implemented in 50GHz f_t SiGe technology achieves 24dBm power output at 1.9GHz [4.2]
  
• Analog broadband-communication circuits can be sucessful in 0.35µm to 0.18µm, CMOS for voltages from 2.5V to 1.0V by utilizing zero-Vt and thick-oxide transistors [4.6]
  
• Analog neural-vision microsystem-on-a-chip performs 1000 images/s in a hand-held OCR using only10mW power [12.1]
  
• 92% fault-detection rate in a 400MHz IEEE-754-compliant floating-point unit for a massively-parallel processor with only 18% area penalty [21.5]
  
• Imaging system for non-contact measurement of clock skew demonstrates 50ps resolution on a Power3 microprocessor [21.7]
  
• 20% to 35% performance gain for SOI versus bulk CMOS [25.1, 25.3]
  
• 25% power reduction for same circuit in SOI versus bulk CMOS [25.5]

APPLICATIONS

• Analog building blocks and integrated ICs for RF communications [4.1, 4.8]
  
• Portable vision, OCR, microdisplay, and chemical-analysis systems [12.1, 12.2, 12.3, 12.5]
  
• Human-implantable prostheses [12.6, 12.7]
  
• High-performance PCs and low-power portable PCs [25.1, 25.7]

ECONOMIC AND SOCIAL IMPACT

• Lower-cost, lower-power, higher-performance RF communications

• Ultra-compact low-power portable microsystems for dedicated applications:
  
  • Optical character recognition; human-face recognition
    
  • Robotic smart-vision; electronic cameras
    
  • Ultra-compact data and image viewing: microdisplay
    
  • Portable chemical and biological analysis

• New generation of wireless "smart prostheses" for disbled humans -- towards the $6M man:
  
  • The "silicon eye"
    
  • The "silicon ear"
    
  • Damaged nerve cell replacement

• New generation of high-performance, power-efficient PCs and consumer electronics based on CMOS SOI ICs

Session: MP4

TECHNOLOGY DIRECTIONS: RF AND ANALOG TECHNIQUES

Chair: Jan Sevenhans, Alcatel, Antwerpen, Belgium
Associate Chair: Khalil Najafi, University of Michgan, Ann Arbor, MI

DRIVERS

• Higher Signal Frequency
  
• Low-Cost
  
• High-Q, Low-Power
  
• Voltage Scaling
  
• Mixed-Mode in Digital Deep-Sub-micron CMOS

HIGHLIGHTS

• SiGe HBT becoming a mainstream process:
  
  • SiGe can be added to a BICMOS process with relatively few additional process steps and masking levels [4.1]
    
  • High yield now being obtained in SiGe HBT technology [4.1, 4.2]
    
  • 1.8M transistor CMOS ASIC integrated with SiGe HBTs in power amplifiers, LNAs, and multiplexers on the same chip [4.1]
    
  • Fully-integrated RF transceiver for DECT demonstrated in a 2-chip SiGe chip set [4.1]
    
  • Future challenges include incorporation of SiGe circuits into automated mixed-signal design, integrating copper interconnect, scaled CMOS and bipolar technology [4.1]

• MEMS components integrated into RF circuits:
  
  • High-Q (~10,000) micromechanical filters demonstrated with 1.25% tunability for use in RF preselect transceivers for Legacy radio applications [4.7]
    
  • 1.9GHz VCO based on micromachined tunable capacitor [4.8]

• High-performance analog and communication circuits can be implementd in deep-submicron digital CMOS:
  
  • Analog communication circuits can be successfully implemented in 0.18µm to 0.35 µmV CMOS for voltages down to 1.0V by utilizing zero-V_t and thick-oxide transistors [4.8]
    
  • Distributed amplifier with 13GHz unity-gain cutoff frequency implemented in 0.18µm, four-metal Al-Cu CMOS [4.3]
    
  • Integrated four-stage distributed amplifier with 6.5dB gain and 5.5GHz bandwidth delivers 85mW at 900MHz utilizing 0.6µm digital CMOS and a single 3V supply [4.4]

• Analog signal processors enable 100x improvement in energy efficiency over programmable DSPs and I0X over a custom DSP:
  
  • 0.5µm CMOS analog coprocessor for 9x9pixel-window template matching achieves data sequencing, 3.6x10⁹ MAC/s, and max-finding, with only 420 MW power. The core analog multipy-accumalators achieve 320MHz operations at 5pJ/multiply-and-odd [4.9]

Session: TP 12

TECHNOLOGY DIRECTIONS: EMERGING MICROSYSTEMS FOR PORTABLE APPLICATIONS

Chair: Woodward Yang, Harvard University, Cambridge, MA
Associate Chair: Jan van der Spiegel, University of Pennsylvania, Philadelphia, PA

DRIVERS

• Low-Power and Single-Chip Systems
  
• Beyond-Silicon Devices: Carbon Nanotube Electronics
  
• Human-Implantable Electronics

HIGHLIGHTS

• Intelligent Imaging Systems
  
  • Optical Character-Recognition System for Handheld Applications [12.1]
    
  • SIMD Processor Array with Integrated Photosensors [12.2]
    
  • Single-Chip Micro-Photospectrometer [12.3]

• Carbon Nanotube Electronics [12.4]

• Low-Power Microdisplay [12.5]

• Human-Implantable Neurostimulators with Wireless Power and Data Transmission [12.6, 12.7]

Session: WA 21

TECHNOLOGY DIRECTIONS: DIGITAL TECHNOLOGIES

Chair: Glenn Gulak, University of Toronto, Toronto, Canada
Associate Chair: Koichiro Ishibashi, Hitachi Ltd., Tokyo, Japan

DRIVERS

• Design Methodologies for System-on-a-Chip
  
• Future Computer Architectures
  
• Reliability of Logic LSI

HIGHLIGHTS

• Intellectual-Property (IP)-Reuse Design [21.1]
  
• Reconfigurable-Computer Design [21.2, 21.3]
  
• Future ESD Protection in Deep-Submicron CMOS [21.4]
  
• Fault-Detecting 400-MHz Floating-Point Unit (FPU) [21.5]
  
• Efficient Embedded-DRAM Controller [21.6]
  
• Skew Observation by Light Emission [21.7]

Session: WP25

CMOS/SOI TECHNOLOGY FOR MICROPROCESSORS, MEMORY, AND LOGIC

Chair: Don Draper, Advanced Micro Devices, Sunnyvale, CA
Associate Chair: Bill Athas, University of Southern California, Marina del Ray, CA

DRIVERS

• Higher clock frequencies
  
• Floating bodies enhance performance of stacked gates
  
• Lower power dissipation
  
• Lower-capacitance junctions and gates
  
• Lower-capacitance metal lines
  
• Less leakage for same drain current
  
• Higher circuit density
  
• No wells

HIGHLIGHTS

• Same yield for a microprocessor in CMOS SOI or bulk CMOS [25.1]
  
• 20 to 35% higher clock frequency in SOI [25.1, 25.3, 25.7]
  
• Reliable SOI substrates available in large quantities [25.2]
  
• New circuit techniques for SOI-specific characteristics [25.3, 25.6, 25.7]
  
• 600 MHz ALPHA^TM processor in fully-depleted SOI [25.4]
  
• 25% less power in 16Mb SOI DRAM [25.5]
  
• Analog circuit methods for 1GHz SOI microprocessor PLL [25.6]