ISSCC 1999 - Conference Overview

• Events
• Plenary Session
• Paper Statistics
• Technical Highlights
• Overseas Panels
• Short Course
• Tutorials

TUTORIALS (Sunday, February 14, 1999)

• Six 90-minute Tutorials, offered three times, taught by circuit experts from the Program Committee, can serve to meet attendees' needs for introductory material in circuit specialties.

WORKSHOP (SUNDAY, FEBRUARY 14, 1999)

• Informal all-day workshop in which circuit experts exchange information on their current research in an interactive environment.

SHORT COURSE (THURSDAY, FEBRUARY 18, 1999)

• Intense all-day Course on a single topic, taught by world-class instructors can serve to "jump start" a change in an engineer's circuit specialty.

TECHNICAL SESSIONS (MON.-WED., FEBRUARY 15-17, 1999)

• Three invited talks presented in the Plenary Session and 170 technical papers presented in 24 Regular Sessions highlight the latest circuit developments.

EVENING DISCUSSIONS (MON. & TUES., FEBRUARY 15-16, 1999)

• Eight Panels in all, where expert panelists debate selected topics and field audience comments and questions in a semi-formal atmosphere.

SOCIAL HOUR (MONDAY, FEBRUARY 15, 1999)

• Network with experts in circuit specialties and meet colleagues in an informal exchange.

[1.1] "THE NEW FRONTIER CREATED BY HIGH-BANDWIDTH DIGITAL-VIDEO SYSTEMS AND SERVICES"
H. Nakatsuka, Toshiba Corporation, Japan

• Interactive TV with 3D capability and intelligent data handling at the viewer site will require LSI circuits with higher bandwidth than is presently available to support HDTV with MPEG2.
  
• A 100M polygon/s processor and 40GB/s memory at the viewer site will enable services such as TV-linked games, virtual shopping malls, and 3D cartoons, without overloading the transmission medium.
  
• Real-time video-image indexing and filtering for the home server will require DSP circuits that are 100 to 1000 times faster than those presently available.

• The computational power of silicon is exploited usually by an increase in clock speed of synchronous digital circuitry. This has given rise to the insatiable demand for bandwidth.
  
• The effects of speed on power dissipation suggest alternatives to brute compute power through architectures exploiting concurrency through parallelism and serialism (pipelining). Flexibility can be addressed with architecture reconfigurability and programability.
  
• The Silicon System Platform concept will allow maximum reuse of hardware and software. It will be illustrated by examples of interactive TV, optical storage, set-top boxes, and handheld communication systems.

H. Samueli, Broadcom, Irvine, California

• High-bandwidth connectivity will affect the way we live and work. Broadband services are being driven by interactive television and the personal computer.
  
• Multimedia-rich data services on the Internet are driving the demand for high-bandwidth remote-access PC connections via cable and xDSL modems. Gigabit Ethernet is being developed to relieve the bandwidth bottleneck created by the explosive growth in network communications worldwide.
  
• Advances in mixed-mode IC integration will be required to satisfy these needs in a cost-effective way. Technologies and designs to meet the ambitious goal of universal broadband connectivity will be presented.

OVERALL

• 316 papers Submitted to ISSCC 99

• 173 Papers Accepted
  
  • 142 Full-Length Papers
    
  • 28 Short Papers
    
  • 3 Plenary Papers

• 25 Paper Sessions in 3 Full Days

• Americas: 50%

• Far East: 30%

• Europe: 20%

• Analog 17 %

• Communications 19 %

• Digital 18 %

• Memory 12 %

• Imagers and MEMS 8 %

• Signal Processing 12 %

• Technology Directions 14 %

ANALOG (Sessions mp3, ta8, wa18, wp23):

• Low-Power Low-Voltage Oversampling Converters [MP3]
  
• High-Precision DACs [TA8]
  
• Fast ADCs [WA18]
  
• Microwave CMOS VCOs [WP23]

• Wireless Circuits for Portable Applications [TP13]
  
• xDSL Signal Processors with Improved Analog Front Ends [TP14]
  
• Clock & Data-Recovery Improvements Lower Jitter [WA20]
  
• Optical Links Moving To Higher Speed and Greater Parallelism [WP22]

• Next-Generation x86 Microprocessor Designs [5.4, 5.6, 5.7]
  
• Gigabit Per Second (Gb/s) Pin Bandwidth [TA10]
  
• First Commercial Processors in SOI [WP25]

• Chain-FRAM Scheme Achieves 37ns Access Time at Half the Previous Cell Size [ 6.1]
  
• High-Bandwidth Primary and Secondary Cache [11.1, 11.2, 11.4, 11.5, 11.6]
  
• Silicon-Implemented Comparison of Direct Rambus DRAM, SLDRAM, and Double-Data-Rate SDRAM Architectures [24.1, 24.2, 24.3, 24.5, 24.7]

IMAGERS AND MEMS (SESSIONS TA7, WA17)]:

• Small-Pixel CCDs [17.1, 17.2]
  
• Sensor Interface Electronics [7.4] and Fingerprint Verification [7.5]
  
• Highly-Integrated CMOS Image Sensors [17.3, 17.4, 17.7]

SIGNAL PROCESSING (SESSIONS MP2, TP14, TP15, WA19):

• Disk-Drive Signal Processing [MP2]
  
• Analog Front-Ends for DSL Systems [TP14]
  
• Video and Multimedia Processors [TP15]
  
• Single-Chip Solutions for Broadband Access and Digital TV [WA19]

• SiGe, Deep-Submicron CMOS, and Micromachining are Driving Advances in RF Communications Circuits [4.1, 4.2, 4.3, 4.4, 4.7, 4.8]
  
• Human-Implantable Neural Stimulation ICs with Wireless Power and Data Transmission Using RF Links [12.6]
  
• Low-Power Systems-on-a-Chip Enable Portable OCR, Vision, Spectrophotometry, and Display [12.1, 12.2, 12.3,12.5]
  
• Reconfigurable Processors Allow Significant Performance Improvements Over Standard Microprocessors and DSPs [21.2, 21.3]
  
• ESD Protection Achieved for Deep-Submicron CMOS Microprocessors [21.4]
  
• Silicon on Insulator (SOI) Comes of Age [WP25]

Panel Session: ME2

OBJECTIVE

• To discuss the feasibility of monochip digital radio.

APPLICATIONS

• Cellular Phones and Wireless LANs

CHALLENGES

• Optimum Cellular Transceiver Architectures
  
• RF + Analog + Digital Integration
  
• Time-to-Market and Cost

CONTROVERSIES

• Single-Mode versus Multi-Mode Radio
  
• Single-Chip versus Single-Package Implementation
  
• Integrated versus Discrete Passive Devices
  

Panel Session: ME2

OBJECTIVE

• To identify a fair mechanism for assigning value to the Intellectual-Property (IP) contribution of designers of blocks in high-integration system chips that motivate IP designers to develop macroblocks generally useful to system LSI designers, while permitting semiconductor foundries to make a fair return on investment.

APPLICATIONS

• Mega-integration System LSIs incorporating third-party IP blocks/circuits

CHALLENGES

• Addressing the needs of system LSI designers while fairly compensating IP-block developers, without unduly burdening the semiconductor companies
  
• Managing multiple IP-block suppliers while maintaining a reasonable profit margin for the semiconductor foundry

CONTROVERSIES

• Who should make the large profit: IP designers, semiconductor foundries, or LSI system designers?
  
• How can foundries afford future investments if their profits are reduced by sharing them with IP designers?
  
• Can long-term mutually beneficial relationships between IP designers and semiconductor foundries be established and maintained, or will there always be an adversarial relationship between them?
  
• Who is really in control of the value of the chip?
  
• Have the semiconductor companies been put into a dependency relationship with the IP suppliers by failing to develop the IP blocks themselves?
  
• Is it helpful for the industry as a whole to have third-party IP developers creating macrocells for system LSI developers instead of the semiconductor foundries offering one-stop shopping?
  
• Should the semiconductor companies act as agents for the IP designers, or should the system LSI designers deal directly with the IP designers?
  
• Will the inclusion of third-party IP blocks into system LSIs limit the choice of semiconductor foundries?
  
• Will a strategic competitive advantage for the semiconductor foundry emerge by aligning with key IP developers?

Time: Thursday after the Conference: February 18, 1999

• Session I: Course 8:00 AM-4:30 PM
  
• Session II: Course 10:00 AM-6:30 PM
  
• Session III: Course 1:30 PM-9:30 PM

This Short Course is intended to jumpstart engineers in the design and development of Gigabit local-area networks (LAN) over four pairs of Category-5 unshielded twisted-pair (UTP) cables. The course will provide an overall perspective of system architectures and specifications, and a detailed description of possible circuit and system designs of 1000BASE-T transceivers. Topics covered include frequency response and noise characteristics of the four-pair CAT-5 UTP transmission medium, cross-talk and echo-cancellation methods, multi-level data detection and error-correction schemes, multi-level clock recovery and phase-locking techniques, and analog interface issues. Emphasis is on CMOS circuit and system implementation.

• S. Rao, Level-One Communications
  
• J. Kenney, Analog Devices, Inc.
  
• B. Kim, Korea Advanced Institute of Science and Technology
  
• B. Ravazi, UCLA

• Implementing Gigabit Ethernet Over CAT-5 Twisted-Pair Cabling (Rao)
  
  • challenges of using CAT-5 unshielded twisted-pair cabling
    
  • system design in the presence of noise environment of CAT-5 UTP
    
  • foundations of 1000BASE-T standard

• Signal Processing and Detection in Gigabit Ethernet (Kenney)
  
  • 1000 Mb/s full-duplex data transfer over UTP
    
  • parallel encoding and detection of data symbols
    
  • crosstalk and echo cancellers, decision-feedback equalizer, Verterbi detector

• PLL/Clock-Recovery Techniques for Fast Local Area Networks (Kim)
  
  • analog, digital, and mixed-mode PLL implementations
    
  • fast locking algorithms and loop-filter optimization for PLLs
    
  • VCO and phase/frequency-detector PLL components

• Analog Interface Issues in Gigabit Ethernet (Razavi)
  
  • twisted-pair and fiber-optic transceivers
    
  • CMOS echo cancellers, equalization, and A/D conversion
    
  • transimpedance amplifiers and clock-recovery circuits

TO - DESIGN METHODOLOGIES FOR INTERCONNECT IN GHZ+ICs
(S.Naffziger, Hewlett-Packard)

T2 - Residential High-Bandwidth Access Technology
(T. Stetzler, Texas Instruments)

T3 - High-Speed CMOS ADCs
(K. Bult, Broadcom)

T4 - Video Compression Circuits
(S. Molloy, Luxxon Corp.)

T5 - Single-Chip CMOS Imaging Systems
(H.-S. Wong, IBM and A. Gamal, Stanford University)

T6 - Signaling in High-Performance Memory Systems
(J. Poulton, University of North Carolina)