ISSCC 1999 - MEMORY

• Summary
• Daytime Paper Sessions
• Evening Panel Discussion
• Tutorial
• Trend Charts

Subcommittee Chair: Bruce Bateman, MicroUnity Systems Engineering, Sunnyvale, CA

HIGHLIGHTS

• Chain-FRAM scheme achieves 37ns access time at half the previous cell size [6.1]
  
• High-Bandwidth Primary and Secondary Cache [11.1, 11.2, 11.4, 11.5, 11.6]
  
• Silicon comparison of Direct Rambus DRAM, SLDRAM, and Double- Data-Rate SDRAM architectures [24.1, 24.2, 24.3, 24.5, 24.7]

MOST-SIGNIFICANT RESULTS

• 256Mb NAND and two-bit-per-cell AND flash implementations [6.5; 6.6]
  
• 18Mb CMOS SRAM with 12.3 GB/s Bandwidth [11.6]
  
• 64Mb DRAM macro results with t_RACs as fast as 6.8ns [24.1, 24.3, 24.4]
  
• 1Gb DDR SDRAMs in 0.14µm CMOS with 67.5% cell/chip area efficiency [24.2, 24.7]

APPLICATIONS

• SRAM Primary and Secondary Cache [11.1, 11.2, 11.4, 11.5, 11.6]
  
• DRAM as main memory in PC, EWS, etc. [24.1, 24.2, 24.3, 24.5, 24.7]
  
• DRAM Macro for embedded solutions [24.4, 24.6]

ECONOMIC AND SOCIAL IMPACT

• Emerging new DRAM architectures are realized in silicon
  
• Storage for improved portable multi-media
  
• Facilitating higher-clock-rate computers

PANEL

• SRAMs in the Early 21^st Century [ME3]

TUTORIAL

• Signaling in High-Performance Memory Systems [T6]

Session: MP 6

FLASH AND FERRO

Chair: Junichi Miyamoto, Toshiba Corp., Yokohama, Japan
Associate Chair: Werner Weber, Siemens AG, Munich, Germany

DRIVERS

• Higher Density Chips
  
• Low-Power Operation
  
• Integration of non-volatile memory with Logic
  
• Fast Random writing with Ferro-Electrics
  
• Quest for non-volatile RAM

HIGHLIGHTS

• Chain-FRAM scheme achieves 37ns access time with half the previous cell size [6.1]
  
• New FRAM cell and sensing architectures address major hurdles with accurate reference and optimal R/W scheme. [6.2, 6.3, 6.4]
  
• 0.25µm NAND flash and two-bit-per-cell AND flash structures realized with similar die sizes [6.5, 6.6]
  
• 16Mb divided-bit-line NOR flash architecture achieves 1.8V operation and Read-While-Write functionality [6.7]
  
• 32kB Flash is integrated with a RISC processor using a combined high- voltage Flash process with a high-performance logic process [6.8]

Session: TA11

HIGH-SPEED SRAM

Chair: BruceBateman, MicroUnity Systems Engineering, Sunnyvale, CA
Associate Chair: Jeffrey Dreibelbis, IBM, Williston, VT

DRIVERS

• Low Latency
  
• High Bandwidth
  
• High Density

HIGHLIGHTS

• 4.8µm² 6T SRAM cell using 0.18µm design rules [11.1]
  
• 700MHz Embedded Cache [11.1]
  
• 1.5MB Embedded Cache [11.2]
  
• 0.18ns BiCMOS ECL Register File [11.3]
  
• Improved SER reliability using an integrated cell capacitor [11.4]
  
• 3.76GB/s 8Mb DDR SRAM with 940Mb/s/pin [11.5]
  
• 12.3GB/s 18Mb Burst SRAM with 1.54Gb/s/pin [11.6]
  

Session: WP24

DRAM

Chair: Adin Hyslop, Micron Technology, Inc., Dallas. TX
Associate Chair: Associate Chair: Tae-Sung Jung, Samsung Electronics, Kyungki-Do, Korea

DRIVERS

• High-Bandwidth for both embedded and stand-alone DRAM
  
• High-Density with advanced process technology
  
• Low-Latency macros for embedded DRAM solutions
  
• Competing architectures for high-performance stand-alone memory

HIGHLIGHTS

• 72Mb Rambus Direct-DRAM implementation results [24.1]
  
• 2.5V 1Gb DDR SDRAM with 0.14µm design rules [24.2]
  
• 72Mb SLDRAM implementation with digitally-calibrated DLL [24.3]
  
• 64Mb DRAM macros with access time as low as 6.8ns [24.4, 24.6]
  
• 1Gb DDR SDRAM with clock-timing generator using 30ps-resolution bidirectional delay element [24.5]
  
• 1Gb DDR SDRAM with 67.5% cell/chip efficiency [24.7]

Panel Session: ME3

SRAMs IN THE EARLY 21^ST CENTURY

OBJECTIVE

• The future of SRAMs as level-2 and level-3 cache.

APPLICATIONS

• Level-2 and level-3 Cache.

CHALLENGES

• Can stand-alone SRAMs offer a low-latency L2 cache solution?
  
• What market incentives remain for stand-alone SRAMs as L2/L3 cache?
  
• Technology scaling limits, economics, and the tracking of Moore's curve.
  
• To embed or not to embed?

CONTROVERSIES

• Is the threat of technology scaling limits real? Are technology, economics, and the tracking of Moore's curve mutually exclusive?
  
• Are there still incentives to market stand-alone SRAMs as L2 & L3 cache?
  
• Are SRAMs still a technology driver? These days maybe CPUs are!
  
• Does the ever-increasing need for embedded SRAM drive stand-alone SRAM into oblivion?
  
• Is embedded SRAM the preferred solution to a tightly-coupled L2 cache?

Tutorial: T6

OVERVIEW

• Transmission line/packaging characteristics and frequency limits
  
• Signaling methods, swings, clocking, references
  
• Comparison of RDRAM, SLDRAM, DDR, and PC100 signaling
  
• Approaches for improving future memory systems

TUTORIAL SPEAKER BIOGRAPHY

John Poulton, Research Professor, Department of Computer Science, University of North Carolina at Chapel Hill, received a BS from VA Tech (1967), MS from SUNY-Stony Brook (1969), and PhD from UNC-Chapel Hill (1980), all in Physics. He has been involved in the design of a series of experimental computer- graphics systems (Pixel-Planes and PixelFlow) at UNC-CH since 1980. His research interests include logic-enhanced memory systems, high-performance signaling, and architectures for graphics and imaging.

Click on the links below to view charts.

• DRAM: Die Size vs. Year
• DRAM/SDRAM: Speed vs. Year
• FLASH MEMORY: Die Size vs. Year
• NON-VOLATILE MEMORY: Cell Size vs. Year
• SRAM: Die Size vs. Year
• SRAM: Speed Size vs. Year