ISSCC 1999 - Executive Summary

• Activities at ISSCC 99
• Conference Theme
• Most-Significant Results

• Short Course presented Thursday, February 18:
  
  • Four linked 90-minute lectures given by experts in the field.

• Tutorials presented Sunday, February 14:
  
  • Six independent lectures selected from each of the ISSCC 99 Program Subcommittees: analog, communications, digital, memory, imagers and MEMS, and signal processing.
    
  • Lectures are presented by expert members each of the Subcommittees

• Technical Paper Sessions presented Monday through Wednesday, February 15-17:
  
  • Three presentations in the Plenary Session on Monday morning
    
  • Twenty-four regular paper sessions beginning Monday afternoon and continuing through Wednesday afternoon
    
    • 142 regular papers
      
    • 28 short papers

• Evening Discussion Sessions presented on Monday and Tuesday evenings:
  
  • Four on each evening

• Social Hour on Monday after the regular paper sessions
  

• The Information Age is characterized by the unquenchable thirst for more and more bandwidth. The increasing use of fast processors, high-speed communications, broadband networks, and highly-parallel signal-processing systems characterizes this fact. The proliferation of high-bandwidth systems has been driven largely by advances in integrated circuits, and is thus a timely theme for ISSCC. Papers spanning each of these topics are included in the 1999 ISSCC.

• Many of the activities and presentations at this year's Conference are focused specifically upon high-bandwidth systems including:
  • Three Plenary Session presentations:
    
    • "The New Frontier Created by High-Bandwidth Digital Video Systems and Services" [MA1.1]
      
    • "Is High-Speed the Only Solution to Exploit the Intrinsic Computational Power of Silicon?" [MA1.2]
      
    • "Broadband Communications ICs: Enabling High-Bandwidth Connectivity in the Home and Office" [MA1.3]

  • Short Course:
    
    • "Fast Local-Area Networks"

  • Technical Paper Sessions:
    
    • "Disk-Drive Signal Processing" [MP2]
      
    • "RF and Analog Technologies" [MP4]
      
    • "Microprocessors" [MP5]
      
    • "Communication Techniques and ATM" [TA9]
      
    • "Clocking and Synchronization" [TA10]
      
    • "High-Speed SRAM" [TA11]
      
    • "Wireless Circuits" [TP13]
      
    • "xDSL Signal Processors"[TP14]
      
    • "Multimedia Processors" [TP15]
      
    • "Nyquist ADCs" [WA18]
      
    • "Clock and Data Recovery" [WA20]
      
    • "Optical Links" [WP22]
      
    • "Analog Techniques II" [WP23]
      
    • "SOI Microprocessors and Memory"[WP25]

• Analog:

  • 1.5V, 1mW Oversampling Converter [3.1]
    
  • 14-bit 100MSample/s CMOS DACs [8.1, 8.2]
    
  • 6-Bit, 500MSample/s CMOS ADCs [18.5, 18.6]
    
  • 2.5GHz BiPolar Equalizer [23.3]
    
  • >5GHz CMOS VCOs [23.6, 23.7, 23.8]

• Communications:

  • Smart RFID [9.1]
    
  • Direct-conversion receiver architectures [13.1, 13.5]
    
  • Optimized analog front-ends for DSL systems [14.2, 14.7]
    
  • 70Mb/s VDSL chip with a new architecture for high-speed computation of FFT/IFFT [14.6]
    
  • Burst-mode PLL for high-capacity crossbar switching [20.1]
    
  • Code- and bit-rate-independent repeaters for flexible fiber infrastructure [20.2, 20.3]
    
  • Improved PLL jitter generation, tolerance, and transfer [20.6]

• Digital:

  • Implemented Instruction Sets for Multimedia and 3D Applications [MP5]
    
  • First Microprocessor with over 100 million Transistors [5.1]
    
  • 600MHz x86 Processor [5.7]
    
  • Spread-Spectrum Clocking Technique Reduces EMI [10.5, 10.6]
    
  • Reduction of Microprocessor Stand-By Current to 18µA [16.4]
    
  • SOI comes of age as a High-Performance Digital-Logic Technology [WP25]
    
  • SOI Processors boost performance by Up to 30% [25.1, 25.3, 25.7]

• Imagers and MEMS:

  • Advancement of Sensor Integration and Interface Circuits [7.1, 7.2]
    
  • Wide-Dynamic-Range CMOS Imagers [17.5]

• Memory:

  • 256 Mb NAND and Two-Bit-Per-Cell AND flash Implementations [6.5, 6.6]
    
  • 18 Mb CMOS SRAM with 12.3GB/s Bandwidth [11.6]
    
  • 64Mb DRAM Macro with t_RACs as fast as 6.8ns [24.1, 24.3, 24.4]
    
  • 1Gb DDR SDRAMs in 0.14µm CMOS with 67.5% Cell/Chip Area Efficiency [24.2, 24.7]

• Signal Processing:

  • Fully Integrated Hard-Disk Drive IC [2.5]
    
  • 70Mb/s VDSL Chip Includes New Architecture for High-Speed Computation of FFT/IFFT [14.6]
    
  • MPEG2 Encoder Chip Includes Video, Audio & System [15.7]
    
  • Mixed-Signal CMOS Digital Satellite-Receiver Chip with 480MHz IF Input [19.1]

• Technology Directions:
  
  • DECT Transceiver Chip Set with Integrated Power Amplifier Implemented in 50GHz f_t SiGe Technology with 24dBm Power Output at 1.9GHz [4.2]
    
  • Analog Communication Circuits in 0.35µm to 0.18µm, 1V CMOS Utilizing Zero-Vt and Thick-Oxide Transistors [4.6]

  • Analog Neural-Vision Microsystem-on-a-Chip Implements 1000 Image/s Hand-Held OCR Using 10mW Power [12.1]
    
  • 92% Fault-Detection Rate in a 400 MHz IEEE-754-Compliant Floating-Point Unit for a Massively-Parallel Processor with Only 18% Area Penalty [21.5]
    
  • Non-Contact Imaging System Achieves 50ps Clock-Skew Resolution on Power3 Microprocessor [21.7]
    
  • 20% to 35% Performance Gain in SOI versus Bulk CMOS [25.1, 25.3]
    
  • 25% Power Reduction for SOI versus Bulk CMOS [25.5]