ISSCC 1999 - Digital

• Summary
• Daytime Paper Sessions
• Evening Panel Discussion
• Tutorial
• Trend Charts

Subcommittee Chair: Ian Young, Intel Corporation, Hillsboro. OR

HIGHLIGHTS

• Next-generation x86 processor designs [5.4, 5.6, 5.7]
  
• Gigabit per second (Gb/s) pin bandwidths [TA10]
  
• First commercial processors in SOI [25.3, 25.4, 25.7]

MOST-SIGNIFICANT RESULTS

• New instruction sets support multimedia and 3D applications [MP5]
  
• First Microprocessor with over 100 million transistors [5.1]
  
• 600MHz x86 processor [5.7]
  
• Spread-spectrum clocking technique reduces EMI [10.5, 10.6]
  
• Reduction of microprocessor stand-by current to 18µA [16.4]
  
• SOI comes of age as a high-performance digital-logic technology [WP25]
  
• SOI processors boost performance by up to 35% [25.1, 25.3, 25.7]

APPLICATIONS

• High-performance processors for personal computers, workstations, servers, and mainframes [MP5]
  
• High-performance, low-power portable computing [MP5, WP25]
  
• High-speed chip-to-chip interconnect [TA10]

ECONOMIC AND SOCIAL IMPACT

• Increased use of digital audio, graphics, and video content in daily life - consumer entertainment, education, communications
  
• Improved human interface - handwriting and speech-recognition technology
  
• Artificial intelligence, expert systems - Medical Care, Finance
  
• Business productivity
  
• Data Mining - access to large databases
  
• Flexible work environment - telecommuting

PANEL

• Best and Worst Innovations in the Evolution of Digital IC Design [ME4]

TUTORIAL

• Design Methodologies for Interconnect in GHz+ ICs [T1]

HOT TOPICS

Why use Silicon on Insulator (SOI)? [WP25]
• Reduced key performance-limiting features of standard bulk Silicon.
  
  • Transistor source/drain capacitances are greatly reduced, resulting in a 25% frequency increase for a microprocessor
    
  • MOS "reverse body effect" is eliminated making stacked- transistor structures much faster

• Remaining challenges for SOI:
  
  • Transistor delay is less predictable (due to the floating body)
    
  • Transistors can have transient parasitic current paths (bipolar effect)
    
  • Manufacturability - SOI Wafer Technology Maturity

Session: MP5

MICROPROCESSORS

Chair: William Bowhill, Compaq Computer Corporation, Shrewsbury, MA
Associate Chair: Kerry Bernstein, IBM Microelectronics, Essex Junction, VT

DRIVERS

• Personal Computers
  
• Multimedia and Visual-Computing applications
  
• General-purpose computing
  
• Workstations
  
• Enterprise Servers and Mainframes

HIGHLIGHTS

• First Microprocessor with over 100 million transistors [5.1]
  
• 600MHz CPU and Memory-System Design for a 12-Processor Mainframe [5.2, 5.3]
  
• 7^th Generation AMD x86 Microprocessor [5.4, 5.5]
  
• New Instruction Sets to support Multimedia and 3D Applications
  [5.4, 5.5, 5.6, 5.7]
  
• First Multimedia-Enhanced PowerPC Microprocessor, achieving 450MHz using Copper Interconnect [5.6]
  
• Next-Generation 600MHz Intel IA-32 Microprocessor [5.7]

Session: TA10

CLOCKING AND SYNCHRONIZATION

Chair: David Greenhill, Sun Microsystems Inc., Palo Alto, CA
Associate Chair: Kevin Donnelly, Rambus Inc., Mountain View, CA

DRIVERS

• High-Speed Clocking Techniques
  
• Electromagnetic-Interference (EMI) reduction
  
• Clock-skew management
  
• Synchronization techniques for chip Interfaces
  
• High-Bandwidth Chip-to-Chip Communications

HIGHLIGHTS

• Gigabit per second (Gb/s) pin bandwidths [10.1, 10.3]
  
• 550MHz and 625MHz system clocks [10.1, 10.3]
  
• Clock-skew management [10.2, 10.4]
  
• Improved clock-signal integrity [10.4]
  
• Spread-spectrum clocking for reduced EMI [10.5, 10.6]

Session: TP15

MULTIMEDIA PROCESSORS

Co-Chair: Vojin Oklobdzjia, Integration, Berkely, CA
Co-Chair: Wanda Gass, Texas Instruments, Dallas, TX

DRIVERS

• Convergence of Computer Entertainment and Consumer Electronics
  
• Writable DVD for digital-video recording
  
• Digital TV and video conferencing (Internet, satellite, cable and HDTV)

HIGHLIGHTS

• Computer/Entertainment Mediaprocessor [15.1, 15.2]
  
• 3-D Geometry Processors achieve GFLOP operation [15.1, 15.3, 15.4]
  
• Video-Codec Datapaths for MPEG or H.263 [15.1, 15.6, 15.7]
  
• Logarithm-domain nonlinear-computing 64-way SIMD [15.4]
  
• Massively-Parallel Image Processing (16Kx64 CAM) [15.5]

Session: TP16

DIGITAL CIRCUIT TECHNIQUES

Chair: Gian Gerosa, Motorola Inc., Austin, TX
Associate Chair: Mike Leary, Chromatic Research, Sunnyvale, CA

DRIVERS

• High Performance
  
• Low Power
  
• Reliability
  
• Mobile Applications

HIGHLIGHTS

• Reliable I/O Buffer Designs for deep-sub-micron processes. [16.1, 16.2]
  
• A high-performance low-power CMOS interface circuit. [16.3]
  
• A 200MHz Microprocessor with Self-Substrate-Biased Data-Retention Mode. [16.4]
  
• Low-power high-performance CMOS circuit-design techniques. [16.4, 16.6, 16.7]
  
• Sense-amplifier-based high-speed logic. [16.5, 16.6]

Session: WP25

CMOS/SOI TECHNOLOGY FOR MICROPROCESSORS, MEMORY, AND LOGIC

Chair: Don Draper, Advanced Micro Devices, Sunnyvale, CA
Associate Chair: Bill Athas, University of Southern California, Marina del Ray, CA

DRIVERS

• Higher clock frequencies
  
  • Lower-capacitance junctions
    
  • Floating bodies enhance performance of stacked gates

• Lower power dissipation
  
  • Lower-capacitance junctions and gates
    
  • Lower-capacitance metal lines

• Less leakage for same drain current

• Higher circuit density
  
  • No wells

HIGHLIGHTS

• Same yield for a microprocessor in CMOS, SOI or bulk [25.1]
  
• 20% to 35% higher clock frequency [25.1, 25.3, 25.7]
  
• Reliable SOI substrates available in large quantities [25.2]
  
• New circuit techniques for SOI-specific characteristics [25.3, 25.6, 25.7]
  
• 600MHz ALPHA^TM processor in fully-depleted SOI [25.4]
  
• 25% less power in 16Mb SOI DRAM [25.5]
  
• Analog-circuit methods for 1GHz SOI microprocessor PLL [25.6]

Panel Session: ME4

THE BEST AND WORST IN THE EVOLUTION OF DIGITAL IC DESIGN

OBJECTIVE

• To discuss the best and worst innovations in the history of digital IC design with a forward-looking perspective on future design challenges.

APPLICATIONS

• Digital-logic IC design, microprocessor circuit design.

CHALLENGES

• Elegant innovations that overcome power, cost, schedule, and technology constraints.
  
• Innovations that provide significant improvements without prohibitive implementation costs.

CONTROVERSIES

• What were the innovations?
  
• Why were they significant?
  
• What problems were being solved?
  
• Was their impact on the industry positive or negative?
  
• How will these innovations impact the future?
  
• What other innovations can we expect in the future?

Tutorial: T1

DESIGN METHODOLOGIES FOR INTERCONNECT IN GHZ+ IC

OVERVIEW

• Specific impacts of interconnect RLC parasitics on GHz designs
  
• Key interconnect-analysis methods and tools
  
• Practical rules-of-thumb to aid the analysis of interconnect designs
  
• Circuit solutions to mitigate the impact of interconnect RLC effects
  
• Repeaters, cross-coupling management, and esoteric signaling methods
  
• Impacts of interconnects on chip microarchitecture

TUTORIAL SPEAKER BIOGRAPHY

Sam Naffziger, Hewlett Packard Engineer/Scientist, Fort Collins, CO, received a BSEE from the California Institute of Technology in 1988 and an MSEE from Stanford in 1993. He has been a technical lead in circuit design on several microprocessors since 1990. Interests include general high-speed circuit techniques, arithmetic circuits, clocking, latching, I/Os, memory, and interconnect design. He holds 8 patents in circuits and in microarchitecture.

MICROPROCESSORS

Click on the links below to view charts.

• Transistor Count vs. Year
• Clock Frequency vs. Year
• ISPEC Performance vs. Year
• ISPEC / Watt vs. Year
• ISPEC / MHz vs. Year