Chair: M. Judy, Analog Devices, Cambridge, MA
Associate Chair: M. Knoll, Sandia National Labs,
Alburquerque, NM
| 7.1 | 2D Magnetic Micro-Fluxgate System with Digital Signal Output | 8:30 AM |
C. Maier, S. Kawahito1, M. Schneider, M. Zimmermann, H. Baltes
Eidgenossische Technische Hochschule, Zurich,
Switzerland
1Toyohashi Univ. of Technology, Toyohashi, Japan
A single-chip CMOS microsystem for two-dimensional magnetic measurements in the
microtesla range (earth's field to 5o angular resolution) is based
on two integrated orthogonal microfluxgate sensors. The chip includes complete
electronics for sensor excitation, sequential signal readout, and A/D
conversion.
| 7.2 | An Interface IC for Capacitive Silicon µg Accelerometer | 9:00 AM |
N. Yazdi, K. Najafi
University of Michigan, Ann Arbor, MI
A switched-capacitor circuit for a capacitive µg accelerometer has 95dB
dynamic range, 370mV input referred offset, and better than 75aF input
capacitance resolution with a 200kHz sampling clock. The IC includes a start-up
circuit and PWM digital lead compensator for closed-loop accelerometer control
with a single 5V supply in a ±1.2g range.
| 7.3 | An SOI, 0.6mV Offset, Temperature-Compensated Hall Sensor Readout IC for Automotive Applications up to 200 o C | 9:30 AM |
M. Schmidt, S. Derksen, H.-L. Fiedler, A. Yasujima1, M.
Matsui1, S. Nagano1, K. Ishibashi2
Fraunhofer Inst. of Microelectronic Circuits and Systems, Duisburg,
Germany
1Asahi Chemical Industry Co., Ltd., Fuji-City,
Japan
2Asahi Kasei Electronics Co., Ltd., Fuji-City, Japan
A high-temperature SIMOX technology with tungsten metallization is used for a
1.7mm2 temperature-compensated Hall-readout IC. The chip is suitable
for automotive applications to 200oC. Automatic offset cancellation
allows continuous operation with 0.6mV offset.
| BREAK | 10:00 AM |
| 7.4 | A Programmable Mixed-Voltage Bus Interface and Sensor Readout with Built-In Self-Test | 10:15AM |
A. Chavan1,2, A. Mason2, U. Kang2,
K. Wise2
1Delphi Delco Electronics Corp., Kokomo,
IN
2University of Michigan, Ann Arbor, MI
A mixed-signal mixed-voltage sensor readout contains a programmable
fully-differential switched-capacitor charge integrator with an on-chip
£30V voltage generator for electrostatic actuation and in-field self-test.
Features include field recalibration, on-chip temperature sensing, and EPROM
storage of calibration data.
| 7.5 | A 15x15mm 2 Single-Chip Fingerprint Sensor and Identifier Using Pixel-Parallel Processing | 10:45 AM |
S. Shigematsu, H. Morimura, Y. Tanabe, K. Machida
NTT, Kanagawa Pref., Japan
An LSI architecture integrates a fingerprint sensor and an identifier in a
single chip and enhances performance of the identifier by pixel-parallel
processing. The sensor is tolerant to electrical, physical, and chemical
degradation. The 15x15mm2 LSI uses 0.5mm standard CMOS.
| 7.6 | A CMOS Micro Touch Pad | 11:15 AM |
N. Manaresi, R. Rambaldi, M. Tartagni, Z. Kovacs, R. Guerrieri
University of Bologna, Bologna, Italy
A direct-contact finger mouse uses 0.7µm digital CMOS. Stroking and
tapping the chip surface with the finger moves a cursor and clicks as with a
standard mouse. Combining analog collective computation and digital processing,
power consumption is ~900µW. The sensor is 3.8x3.8mm2, and the
overall chip is 7.7x6.7mm2.
| 7.7 | A 100Frames/s CMOS Active Pixel Sensor for 3D-Gesture Recognition System | 11:30 AM |
H. Miura, H. Isiwata, Y. Iida, Y. Matunaga
Toshiba Corp., Kawasaki, Japan
A CMOS active-pixel sensor with two capacitor cells, on-chip differential
circuits and ADC is developed using a 0.6µm CMOS. The process performs a
3D object extraction at 100frames/s with light-emitting diodes as the active
illumination source.
| CONCLUSION | 11:45 AM |
Chair: T. Wakimoto, NTT System Electronics Labs,
Kanagawa, Japan
Associate Chair: P. Hurst, University of California, Davis, CA
| 8.1 | A 14b 150MSample/s Update Rate Q 2 Random Walk CMOS DAC | 8:30 AM |
J. Vandenbussche, G. Van der Plas, A. Van den Bosch, W. Daems, G. Gielen, M.
Steyaert, W. Sansen
Katholieke Universiteit Leuven, Heverlee, Belgium
A 14b 150MSample/s current-steering DAC uses Q2 random-walk
switching to achieve 0.3lsb INL and 84dB SFDR at 500kHz, with 300mW power
consumption from a single 2.7V supply. No trimming or tuning is required. Die
area is 13.1mm2 in 0.5µm single-poly CMOS.
| 8.2 | A 14b 100MSample/s CMOS DAC Designed for Spectral Performance | 9:00 AM |
A. Bugeja, B.-S. Song, P. Rakers1, S. Gillig1
University of Illinois, Urbana, IL
1Motorola Inc., Schaumburg,
IL
A CMOS DAC for spectral performance uses a nonlinearity-reducing output stage
to reduce harmonics. The 14.4mm2 externally-trimmed DAC consumes
750mW from 5V at 100MSample/s in 0.8µm CMOS.
| 8.3 | A 110dB THD, 18mW DAC Using Output Sampling and Feedback to Reduce Distortion | 9:30 AM |
A. Thomsen, D. Kasha, L. Wang, W. Lee
Crystal Semiconductor Div., Cirrus Logic, Inc., Austin, TX
A 1b DAC and LPF architecture reduce distortion from settling at the interface
between discrete and continuous time through feedback. The critical circuit is
the first switched-capacitor integrator. THD is -110dB, SNR is -114dB in 400Hz
with 1MHz sampling, and out-of-band noise is
<-50dB using one external capacitor.
| BREAK | 10:00 AM |
| 8.4 | A Multi-bit [Sigma][Delta] Audio DAC with 120dB Dynamic Range | 10:15 AM |
I. Fujimori, A Nogi, T. Sugimoto
AKM Design Tek, San Diego, CA
A 5V stereo DAC for consumer audio has 120dB dynamic range over 20kHz
bandwidth and consumes 290mW. The 3rd-order [Sigma][Delta] DAC employs a 5b SC
DAC with CS LP and FIR filters to increase jitter tolerance. Partial
data-weighted averaging enhances shaping of mismatches in the DAC. The
7.8µm2 chip uses 0.5µm CMOS.
| 8.5 | PowerDAC: A Single-Chip Audio DAC with 70%-Efficient Power Stage in 0.5µm CMOS | 10:45 AM |
K. Philips, J. van den Homberg, E. Dijkmans
Philips Research Labs. Eindhoven, The Netherlands
A bitstream D/A converter with power output stage in 0.5µm CMOS with 5V
supply delivers over 1Wrms to a 8[Omega] loudspeaker. The
single-chip power DAC achieves <0.1% THD at 1kHz and 1Wrms, 84dB
SNR in 20kHz bandwidth, 90dB PSRR and 70% efficiency at maximum output power.
| 8.6 | A DC/DC Converter Using Divided Switches with Current Control Technique | 11:15 AM |
S. Sakiyama, J. Kajiwara, M. Kinoshita, K. Satomi, K. Ohtani,
A. Matsuzawa
Matsushita Electric Industrial Co., Ltd., Kyoto, Japan
A dc/dc converter uses divided switches with current control to achieve 92%
efficiency. The output is programmable from 1 to 2.5V with ~30mV peak output
noise. The converter occupies 0.46mm2 in 0.25µm CMOS and
operates from a 3.3V supply.
| 8.7 | Damping Factor Control Frequency Compensation Technique for 2V Low-Power Large- Capacitative-Load Applications | 11:30 AM |
K.-N. Leung, P. Mok, W.-H. Ki, J. Sin
Hong Kong Univ. of Science and Technology, Kowloon, Hong Kong
Frequency compensation enhances the gain-bandwidth of a 3-stage amplifier for
low-voltage low-power large-capacitive-load applications. Using a 0.8µm
CMOS process, >100dB gain amplifiers with 2.6MHz GBW at 25k[Omega], 100pF
load and 1MHz GBW at 25k[Omega], 1nF load are obtained.
| CONCLUSION | 11:45 AM |
Chair: C. Chien, Rockwell Science Center, Thousand Oaks, CA
Associate Chair: Y. Oowaki, Advanced Semiconductor Devices Res. Lab.,
Kawasaki, Japan
| 9.1 | A 13.56MHz CMOS RF Identification Transponder IC with Dedicated CPU | 8:30 AM |
S. Masui, E. Ishii, T. Iwawaki, Y. Sugawara, K. Sawada
Nippon Steel Corp., Kanagawa, Japan
A RF identification transponder IC achieves up to 212kb/s data rate at 13.56MHz
interrogating magnetic field. A dedicated 12b CPU controls data rate, power
consumption and anti-collision ID readout. Integrated with 1kx12b ROM and
2kx12b EEPROM in 0.8µm CMOS technology, the IC occupies 11mm2
and dissipates 2mW.
| 9.2 | A CMOS Dual Channel 100MHz-1.1GHz Transmitter for Cable Applications | 9:00 AM |
M. Borremans, C. De Ranter, M. Steyaert
Katholieke Universiteit Leuven, Heverlee, Belgium
A 1.25x1.25mm2 dual-channel cable transmitter in standard 0.5µm
3.3V CMOS operates from 100MHz to 1.1GHz. All distortion or intermodulation
products are below -40dBc. Each channel delivers -16dBm output signal to a
75[Omega] double-terminated load. Multiple transmitters are combined without
signal loss or additional power consumption using single-ended RF current-based
output drivers.
| 9.3 | A BiCMOS 300ns Attack-Time AGC Amplifier with Peak-Detect and Hold for High-Speed Wireless ATM Systems | 9:30 AM |
T. Drenski, L. Desclos, M. Madihian, H. Yoshida1, H.
Suzuki1, T. Yamazaki1
NEC Corp., Kawasaki, Japan / 1Kanagawa, Japan
A 0.25µm BiCMOS AGC amplifier with on-chip peak-detect and hold for
high-speed wireless ATM achieves a typical dynamic range of 45dB at 400MHz. The
2.3x1mm2 device achieves a 300ns attack-time and exhibits constant
noise figure <10dB over 30dB of gain control with 52mW power consumption at
3V.
| BREAK | 10:00 AM |
| 9.4 | A 622Mb/s CMOS ATM Switch Access LSI with Maintenance Cycle Interleaved Pipeline Architecture | 10:15 AM |
T. Saito, Y. Shimojo, T. Nagamatsu, J. Hasegawa, T. Fujisawa,
Y. Miyama2, N. Yoshida2, Y. Oyamada2, H.
Irie2, K. Shinohara2,
Y. Hanagama2, K. Sakaue1, K. Satoh1, H.
Hayashida, H. Baba,
H. Matsushita2, S. Nomura, Y. Miyazawa, A. Kanuma
Toshiba Corp., Kawasaki, Japan
1Toshiba Microelectronics Corp.,
Kawasaki, Japan
2Toshiba Information Systems Corp., Kanagawa,
Japan
An ATM switch access chip supports scalability to 20Gb/s switch fabric, 5 QoS
classes, policing/traffic shaping, and OAM/RM cell processing. The chip
implements maintenance cycle interleaved pipeline architecture to accomodate
the RAM data integrity and maintenance processing. The chip integrates 2.4M
transistors in 14.98x14.98mm2 with 0.3µm triple-metal CMOS, and
is housed in a 576pin BGA.
| 9.5 | A 622Mb/s 256k ATM Resource-Management Circuit | 10:45 AM |
P. Gallay, J. Majos, M. Servel1
France Telecom, Grenoble, France / 1Lannion, France
A resource-management chip in 0.5µm CMOS for 622Mb/s ATM applications
solves the cell multiplexing spacing problem allowing for any number of
connections, burst shaping with a maximum of 256k cell time. The
13.4x12.9mm2 device achieves a 50MHz clock rate and consumes 0.6W at
3.3V.
| 9.6 | A 10Gb/s (1.25Gb/sx8) 2x4 CMOS/SIMOX ATM Switch | 11:15 AM |
E. Oki, N. Yamanaka, Y. Ohtomo
NTT, Tokyo, Japan
A 16.6x16.6mm2 10Gb/s 4x2 ATM switch LSI employs distributed
contention control that makes the LSI scalable up to 640Gb/s. Power consumption
of 7W and 1.25Gb/s per pin throughput are achieved with 0.25µm CMOS/SIMOX
at -2V supply voltage.
| CONCLUSION | 11:30 AM |
Chair: D. Greenhill, Sun Microsystems, Palo Alto, CA
Associate Chair: K. Donnelly, Rambus, Inc., Mountain View, CA
| 10.1 | 110GB/s Simultaneous Bi-Directional Transceiver Logic Synchronized with a System Clock | 8:30 AM |
T. Takahashi, T. Muto, Y. Shirai, F. Shirotori, Y. Takada, A. Yamagiwa, A.
Nishida, T. Kiyuna
Hitachi, Ltd., Tokyo, Japan
A 110GB/s simultaneous bi-directional transceiver logic, for 0.25µm CMOS
embedded array, has a low-voltage swing input flip-flop circuit and an output
flip-flop with boundary scan to enable 1.1Gb/s data transfer per LSI pin with
550MHz system clock. Low-noise output buffer and refined package achieve 100B
data bus.
| 10.2 | A 750Mb/s 0.6µm CMOS Two-Phase Input Port Using Self-Tested Self-Synchronization | 9:00 AM |
F. Mu, C. Svensson
IFM, Linköping University, Linköping, Sweden
As clock frequency on silicon chips increases, clock phase becomes difficult to
control or predict. A self-tested self-synchronization is implemented by a
two-phase input port for parallel/series data transfer between modules. In
0.6µm CMOS, data rate is 750Mb/s, with 3.6V supply. Synchronization uses
timing between local clock and incoming data.
| 10.3 | A 2B Parallel 1.25Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking | 9:30 AM |
K. Gotoh, H. Tamura, H. Takauchi, T.-s. Cheung, W. Gai1, Y.
Koyanag1, R. Schober1, R. Sastry1, F.
Chen1
Fujitsu Labs., Ltd., Kawasaki, Japan
1 HAL Computer Systems,
Campbell, CA
A parallel 1.25Gb/s bandwidth 7.7ns latency I/O transceiver for scalable
multiprocessor system uses 0.25µm CMOS. The link supports plesiochronous
clocking using phase-interpolator-based clock recovery and tolerates up to
6.4ns inter-wiring skew with de-skew circuitry. DPRD achieves low latency
equalization for up to 10dB skin-effect cable loss.
| BREAK | 10:00 AM |
| 10.4 | Low-Skew Clock Generator with Dynamic Impedance and Delay Matching | 10:15 AM |
A. Balastos, D. Lewis
University of Toronto, Toronto, Canada
A multiple-output clock generator chip contains impedance locked loop and delay
locked loop for each clock signal generated. The chip uses time-domain
reflectometry to dynamically track impedance and delay of the PCB wire to
compensate for process variation and environmental drift.
| 10.5 | Dual-Loop Spread-Spectrum Clock Generator | 10:45 AM |
H.-S. Li, Y.-C. Cheng, D. Puar
NeoMagic Corp., Santa Clara, CA
A spread-spectrum clock generator has master PLL and slave modulation-locked
loop. The slave generates saw-tooth modulation to the master and tracks PLL
phase comparison timing and control node voltage. The resulting EMI reduction
of peak noise power is 11.2dB.
| 10.6 | Clock Dithering for Electromagnetic Compliance Using Spread-Spectrum Phase Modulation | 11:15 AM |
Y. Moon, D.-K. Jeong, G. Kim1
Seoul National University, Seoul, Korea
1Silicon Image,
Cupertino, CA
Spread-spectrum phase modulation of a system clock that reduces spectral peaks
of EMI emissions is implemented with a DLL and a VCDL to control clock period
variation within 3.3%. CISPR16-1 EMI measurement shows spectral peaks reduced
by 10dB for a 130MHz prototype system with 8b parallel lines. The DLL frequency
range is imkproved up to 7:1.
| CONCLUSION | 11:45 AM |
Chair: B. Bateman, MicroUnity Systems Engineering,
Sunnyvale, CA
Associate Chair: J. Dreibelbis, IBM, Williston, VT
| 11.1 | A 1.4ns Access 700MHz 288kb SRAM Macro with Expandable Architecture | 8:30 AM |
H. Shimizu, K. Ijitsu, H. Akiyoshi, H. Takatsuka, K. Watanabe,
K. Aoyama, R. Nanjo, Y. Takao
Fujitsu, Ltd., Kawasaki, Japan
A 1.4ns-access 700MHz 288kb embedded SRAM macro in 0.18µm CMOS uses a
pulsed decoder and two-stage sense amplifier (current sense/voltage sense). A
4.8µm2 6-T cell results in a 2.19mm2 macro. The RAM
macro is expandable without speed loss.
| 11.2 | A 500MHz 1.5MB Cache with On-Chip CPU | 9:00 AM |
J. Lachman, J. Hill
Hewlett-Packard, Fort Collins, CO
A 500MHz four-way-set-associative on-chip 1.0MB data cache and 0.5MB
instruction cache allow a single cycle access with up to three stores or loads
executed every cycle. Aggregate cache bandwidth is 16GB/s. The cache uses
0.25µm CMOS with 5 metal levels.
| 11.3 | A 0.18ns 32-Wordx32b Three-Port Bipolar Register File Implemented Using a SiGe HBT BiCMOS Technology | 9:30 AM |
S. Steidl, J. McDonald
Rensselaer Polytechnic Institute, Troy, NY
A 32-wordx32b register file with 2 read ports and 1 write port uses SiGe HBT
BiCMOS technology. Access time is 0.18ns with 5.8W estimated power dissipation
using a 4.5V supply.
| BREAK | 10:00 AM |
| 11.4 | A 500MHz Pipelined Burst SRAM with Improved SER Immunity | 10:15 AM |
T. Wada, S. Ohbayasi, H. Sato, K. Kozaru, Y. Okamoto, Y. Higaside, T.
Shimizu, Y. Maki, R. Morimoto, H. Otoi, T. Koga, H. Honda,
M. Taniguchi, Y. Arita, T. Shiomi
Mitsubishi Electric Corp., Itami, Hyogo, Japan
A 64kx36b pipelined burst SRAM achieves 500MHz frequency at 3.3Vand 25°C.
The device has a 6.156µm2 cell and occupies
30.77mm2. Addition of a stacked capacitor improves SER 3.5 orders of
magnitude.
| 11.5 | A 940MHz Data Rate 8Mb CMOS SRAM | 10:45 AM |
G. Braceras, A Roberts, J. Connor, R. Wistort, T. Frederick, M. Robillard,
S. Hall, S. Burns, M. Graf
IBM Microelectronics, Essex Jct., VT
An 8Mb CMOS RAM cycles at 470MHz and provides 940MHz data rate under ambient
conditions. The cell and array are 8.64µm2 and
137.6µm2 respectively in a 0.21µm technology.
Self-resetting circuits give latencies down to 3.6ns. A separate redundant
array minimizes latency.
| 11.6 | An 18Mb, 12.3GB/s CMOS Pipeline-Burst Cache SRAM with 1.54Gb/s/pin. | 11:15 AM |
C. Zhao, U. Bhattacharya, M. Denham, J. Kolousek, Y. Lu, Y.-G. Ng, N.
Nintunze, K. Sarkez, H. Varadarajan1
Portland Technology Development, Intel Corp., Hillsboro, OR
1MPG,
Intel Corp., Hillsboro, OR
An 18Mb CMOS pipeline-burst cache SRAM achieves 12.3GB/s data transfer with
1.54Gb/s/pin I/Os using a source-synchronous I/O interface, reduced-swing
output buffer, and high-bandwidth input buffer. The 14.3µm2
chip uses a 5.6µm2 6-T cell in a 0.18µm 6-metal-layer
technology.
| CONCLUSION | 11:45 AM |
Chair: W. Yang, Harvard University, Cambridge, MA
Associate Chair: J. van der Spiegel, University of
Pennsylvania, Philadelphia, PA
| 12.1 | 10mW CMOS Sensor and Classifier for Handheld 1000 Image/s Optical Character-Recognition | 1:30 PM |
P. Masa, P. Heim, E. Franzi, X. Arreguit, F. Heitger, P-F. Ruedi,
P. Nussbaum, P. Pilloud, E. Vittoz
CSEM, Centre Suisse d'Electronique et de Microtechnique SA, Neuchatel,
Switzerland
A CMOS 10mW retina and a 1mW classifier for a 1000 images-per-second optical
character-recognition system processes fonts of different types and size in
real time, tolerates distortions, low contrast, and illumination inhomogeneity,
which makes it particularly suited for widespread portable applications.
| 12.2 | A CMOS Vision Chip with SIMD Processing-Element h5 Array for 1ms Image Processing | 2:00 PM |
M. Ishikawa, K. Ogawa, T. Komuro, I. Ishii
University of Tokyo, Tokyo, Japan
Massively-parallel processing uses a compact general-purpose processing-element
array integrated with photo detectors. Each 522-transistor pixel occupies
150µm2 using a standard 0.35µm CMOS process. Architecture,
a fabricated chip, and applications are described.
| 12.3 | On-Chip Integrated CMOS Optical Microspectrometer with Light-to-Frequency Converter and Bus Interface | 2:30 PM |
G. de Graaf, J. Correia, M. Bartek, R. Wolffenbuttel
Delft University of Technology, Delft, The Netherlands
A fully-integrated 3.9x4.2mm2 micro-spectrometer uses 1.6µm
CMOS. Compatible post-processing is used to fabricate an array of Fabry-Perot
etalons, tuned for different resonance in a range of 400-500nm (FWHM=18nm). A
light-to-frequency converter, with 75HzµW-1cm2
sensitivity and 105 dynamic range, and a bus interface are included.
| BREAK | 3:00 PM |
| 12.4 | Electronics of Single-Wall Carbon Nanotubes | 3:15 PM |
A. Johnson
University of Pennsylvania, Philadelphia, PA
Single-wall nanotubes can be conductors or semiconductors depending on their
geometry. Devices made from these molecules include transistors, quantum-effect
single-electron transistors, and single-tube junctions. Measured
characteristics of FETs and potential applications are covered.
| 12.5 | A 160x120 Pixel Liquid-Crystal-on-Silicon Microdisplay with an Adiabatic DAC | 3:45 PM |
M. Ammer, M. Bolotski1, P. Alvelda1, T. Knight
MIT, Cambridge, MA
1MicroDisplay Corp.
A 160x120-pixel liquid-crystal-on-silicon microdisplay has 25µm pixels in
a 0.8µm 3-metal process. The die integrates 6b sampled-ramp DAC drivers
that support adiabatic and energy-recovery operation. The display operates in a
twisted-nematic LC mode and consumes 6.3mW at 4MHz and 5V.
| 12.6 | A Wireless Single-Chip Telemetry-Powered Neural-Stimulation System | 4:15 PM |
J. Von Arx, K. Najafi
University of Michigan, Ann Arbor, MI
A 3.1k-transistor BiCMOS chip integrates an on-chip high-Q electroplated copper
coil with a ferrite core for receiving power and data through a 4MHz RF
carrier. It delivers 20mW dc power through a 4V supply, decodes amplitude and
pulse-width modulated data, selectively delivers a 5b programmable 2mA biphasic
current pulse through any pair of 16 stimulating electrodes, and consumes
15mW.
| 12.7 | An Implantable Neuro-Stimulator Device for a Retinal Prothesis | 4:45 PM |
M. Clements, K. Vichienchom, W. Liu, E. McGucken, C. DeMarco,
C. Hughes, J. Mueller
North Carolina State University, Raleigh, NC
When retinal photoreceptors do not produce sufficient neural signals in
response to light, it is possible to create visual sensation by direct
electrical stimulation of retinal tissue. A prosthesis in 1.2µm CMOS
recovers power and data from an inductively-coupled link and provides
neuro-stimulus current-pulse signals for 100 retinal electrodes.
| CONCLUSION | 5:15 PM |
Chair: J. Long, University of Toronto, Toronto, Canada
Assoc. Chair: J. Khoury, Lucent Technologies, Allentown, PA
| 13.1 | A Wide-Band Direct Conversion Receiver for WCDMA Applications | 1:30 PM |
A. Pärssinen, J. Jussila, J. Ryynanen, L. Sumanen, K. Halonen
Helsinki University of Technology, Helsinki, Finland
A direct-conversion receiver chip set for Wideband CDMA communications provides
96.5dB gain with 78dB control range. The receiver achieves 5.3dB NF, -9.5dBm
IIP3, and +38dBm IIP2 giving -114dBm RF sensitivity for 128kb/s data rate at
4.096Mchips/s. In 25GHz 0.35µm BiCMOS, it dissipates 285mW from 2.7V
supply.
| 13.2 | A 22mW NADC Receiver IF Chip with Integrated Second IF Channel Filtering | 2:00 PM |
A. Montalvo, A. Holden, W. Suter, C. Angell, S. White, N. Klemmer,
D. Homol
Ericsson, Inc., Research Triangle Park, NC
A receiver IF chip with integrated Gm-C second IF channel filter achieves 70dB
spurious-free dynamic range and includes a received signal strength indicator
with >100dB dynamic range. The chip occupies 8.3mm2 in a
0.8µm BiCMOS technology and consumes 8.5mA from a 2.6V supply.
| 13.3 | Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications | 2:30 PM |
K. Fong
Phillips Semiconductors, Sunnyvale, CA
0.9GHz low-band and 1.96GHz high-band low-noise amplifiers achieve 1.5dB and
1.9dB noise figure and -1dBm and3 dBm IP3 respectively. Gains are controlled in
discrete steps using resistor-chain networks. Shunt-feedback gives linearity
in the low-band amplifier. The 3V chip dissipates 14mW per LNA in 0.5µm
CMOS.
| BREAK | 3:00 PM |
| 13.4 | 2.1GHz Direct-Conversion GaAs Quadrature Modulator IC for W-CDMA Base Station | 3:15 PM |
J. Itoh, M. Nishitsuji, O. Ishikawa, D. Ueda
Matsushita Electronics Corp., Osaka, Japan
A 2.1GHz direct-conversion GaAs QMOD IC for W-CDMA base station with
active-phase shifter using 4.2GHz 1/2-frequency divider and a low-distortion
mixer achieves -60dBc carrier-leakage ratio and -60dBc ACPR using 0.2µm
double-delta-doped MODFET with STO capacitor. The 1.7mm2 IC
dissipates 350mW at 5V.
| 13.5 | A Single-Chip CMOS Direct-Conversion Transceiver for 900MHz Spread-Spectrum Digital Cordless Phones | 3:30 PM |
T. Cho, E. Dukatz, M. Mack, D. MacNally, M. Marringa, S. Mehta,
C. Nilson, L. Plouvier, S. Rabii
Level One Communications, San Francisco, CA
A transceiver comprising RF circuits, synthesizer, baseband filters,
demodulator, and digital burst-mode controller integrates all signal processing
between antenna and codec with few external components. The 36mm2
0.6µm CMOS IC provides -104dBm sensitivity and draws 160mA during RX and
77mA during TX from 3.3V.
| 13.6 | A Monolithic 3.7W Silicon Power Amplifier with 59% PAE at 0.9GHz | 4:00 PM |
W. Simbürger, H.-D. Wohlmuth, P. Weger
Siemens AG, Munich, Germany
A monolithic RF power amplifier for 0.8-1GHz uses 25GHz-fT
0.8µm Si bipolar technology. The balanced 2-stage power amplifier uses
on-chip transformers as input balun and for interstage matching. Maximum output
power is 3.7W and maximum efficiency is 59%. The chip operates from 2.7V to
4.5V. The linear gain is 35dB.
| 13.7 | A 20mA-Receive, 55mA-Transmit, Single-Chip GSM Transceiver in 0.25µm CMOS | 4:30 PM |
P. Orsatti, F. Piazza, Q. Huang, T. Morimoto1
Swiss Federal Institute of Technology, Zurich,
Switzerland
1Toshiba Corp., Tokyo, Japan
A single-chip GSM transceiver IC in 0.25µm CMOS contains a superheterodyne
RX with 8.1dB SSB niose figure, -10dBm IIP3, and a 71MHz IF. The direct
up-conversion TX has +3dBm output. Current consumption in Rx is 20mA and 55mA
in TX
| 13.8 | A 1.8V 14b Audio Front-End Codec for Digital Cellular Phones | 5:00 PM |
S. Pernici, C. Pinna, C. Condemi, P. Confalonieri, A Nagari,
G. Nicollini
ST-Microelectronics, Agrate Brianza, Italy
A 1.8V 7mW audio front-end for the new generation of portable phones includes a
14b uniform [Sigma][Delta] codec with channel filters and high-performance
speech interfaces. The full-scale S/(N+D) ratios are 77dB for the A/D and 80dB
for the D/A. The area is 2.7mm2 in 0.35µm 5-metal double-poly
CMOS.
| CONCLUSION | 5:30 PM |
Co-Chair:
L. Thon, IBM Almaden Research Ctr., San Jose, CA
| 14.1 | A 0.5µm CMOS ADSL Analog Front-End IC | 1:30 PM |
J. Cornil, Z. Chang, F. Louagie, W. Overmeire, J. Verfaille
Alcatel Bell, Antwerp, Belgium
A 0.5µm CMOS analog front-end IC for ADSL contains an ADSL transceiver
with analog transmit and receive functions. The IC includes trimming-free 3.3V
8.8MSample/s 13b pipeline A/D and 12b current-steered D/A converters, linear
continuous time filters, PGAs, VCO, DAC and crystal driver. The
30mm2 IC uses 0.5µm double-poly triple-metal CMOS and
dissipates 400mW using a 3.3V supply.
| 14.2 | A CMOS Analog Front-End IC for DMT ADSL | 2:00 PM |
C. Conroy, S. Sheng, A. Feldman1, G. Uehara2, A.
Yeung, C.-J. Hung, V. Subramanian, P. Chiang3, P. Lai, X. Si, J.
Fan, M. Flynn
DataPath Systems, Inc., Los Gatos, CA
1Level One Communications,
San Francisco, CA
2 University of Hawaii at Manoa, Honolulu,
HI
3Stanford University, Stanford, CA
A 5V 14b linear analog front-end for T1E1.413 DMT ADSL supports FDM, analog
echo-cancellation, G.lite, and ADSL over ISDN. The 32.8mm2
0.5µm CMOS IC uses digitally-calibrated ADC and DAC and digitally-tuned CT
filters. Power is 1.05W (FDM mode), or <600mW with 6 - 10dB linearity
reduction. Input-referred noise is -160dBm/Hz at 300kHz.
| 14.3 | CODEC for Echo-Cancelling Full-Rate ADSL Modems | 2:30 PM |
R. Hester, S. Mukherjee, D. Padgett, D. Richardson, W. Bright,
M. Sarraj, M. Agah, A. Bellaouar, I. Chaudhry, J. Hellums, K. Islam,
A. Loloee, J. Nabicht, F. Tsay, G. Westphal
Texas Instruments, Dallas, TX
An ADSL CODEC in 3.3V CMOS provides complete low-voltage transmitter and
receiver analog interfaces between DSP and subscriber loop for either central
office (ATU-C) or remote terminal (ATU-R), selectable by metal mask option. Die
area is 67.5mm2. Power dissipations are 600mW (ATU-C), and 760mW
(ATU-R).
| BREAK | 3:00 PM |
| 14.4 | A 25kft 768kb/s CMOS Transceiver for Multiple Bit-Rate DSL | 3:15 PM |
M. Mojal, M. Groepl, T. Blon
Siemens AG, Munich, Germany
A transceiver for multi-bit-rate digital subscriber loop (MDSL) transmits up to
25kft over AWG 24 wire. The IC contains multi-bit [Sigma][Delta]-DAC with
"hopping" dynamic elements, [Sigma][Delta]-ADC, nested Miller line driver, and
-30dB rejection hybrid filter. The concept is tested for ADSL rates. The
12mm2 0.5µmCMOS chip dissipates 250mW at 3V.
.
| 14.5 | An Integrated Analog Front-End for VDSL | 3:45 PM |
N. Sands, E Naviasky1, B. Evans1, M.
Mengele1, K. Faison1, C. Frost1, M.
Casas1, M. Williams1
Texas Instruments Broadband Access Group, San Jose, CA
1Cadence
Spectrum Design, Columbia, MD
A mixed-signal IC incorporates analog front-end functions for VDSL modem using
synchronized discrete multi-tone linecode. The IC contains 11b DACs,
line-driver interface, programmable-gain receive amplifier, rf interference
canceller, compromise equalizer, ADC, numerically-controlled crystal
oscillator, and tone detector. In 0.35µm CMOS DPTM it consumes 550mW at
22.08MHz sample rate with single 3.3V supply.
| 14.6 | A 70Mb/s Variable-Rate DMT-Based Modem for VDSL | 4:15 PM |
D. Veithen, P. Spruyt, T. Pollet, M. Peeters, S. Braet, O. Van de Wiel, H.
Van De Weghe
Alcatel, Antwerp, Belgium
A chip integrates digital signal processing required by a TDD-DMT VDSL system
and transport convergence sublayer functions. The chip processes a 512-point
real FFT/IFFT in <20µs. A fully-programmable RS encoder/decoder and
(de)interleaver provides error-correction. The 150mm2 chip in
0.35µm CMOS dissipates 2.7W at 3.3V.
| 14.7 | A 52Mb/s Universal DSL Transceiver IC | 4:45 PM |
R. Joshi, P. Yang, H.-C. Liu, K. Kindsfater, K. Cameron, D. Gee,
H. Vu, G. Gorman, S. Tsai, A. Hung, R. Khan, V. Hue, O. Lee,
D. Jones, H. Samueli
Broadcom Corp., Irvine, CA
A twisted-pair QAM transceiver IC accomodates data rates to 52Mb/s and supports
4-, 16-, 32-, 64-, 128-, and 256-QAM formats at rates to 13MBaud. The device
incorporates a 10b A/D converter, a 10b D/A converter and analog PLLs for clock
generation and contains a complete modulator and receiver, with Reed-Solomon
forward error correction and ATM Utopia input and output interfaces. The
1.05M-transistor transceiver in 0.35µm four-level metal single-poly CMOS
occupies 33.4mm2.
| 14.8 | An Integrated Adaptive Analog Balancing Hybrid for (A)DSL Modems | 5:15 PM |
F. Pécourt, J. Hauptmann, A. Tenen1
Siemens Semiconductor Group, Villach, Austria
1ECI Telecom Ltd.,
Tel Aviv, Israel
A fully-integrated balancing hybrid for ADSL modems with overlapping frequency
transmission bands automatically adjusts to all different line types and
lengths and reduces the receive-path echo by at least 26dB. The 4mm2
0.6µm CMOS chip dissipates 150mW from 5V.
| CONCLUSION | 5:30 PM |
Chair: V. Oklobdzjia, Integration, Berkeley, CA
Associate Chair: W. Gass, Texas Instruments, Dallas, TX
| 15.1 | A Microprocessor with 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and MPEG2 Decoder | 1:30 PM |
K. Kutaragi, S. Okamoto, M. Suzuoki, T. Hiroi, M. Oka, A Ohba,
Y. Yamamoto, M. Furuhashi, M. Tanaka, T. Yutaka, T. Okada,
H. Magoshi, M. Nagamatsu1, Y. Urakawa1, M.
Funyu1, A. Kunimatsu1,
H. Goto1, K. Hashimoto1, N. Ide1, H.
Murakami1, Y. Ohtaguro1, A. Aono2
Sony Computer Entertainment, Inc., Tokyo, Japan
1Toshiba Corp.
/ 2Toshiba Microelectronics Corp., Kawasaki, Japan
A 250MHz microprocessor consists of a CPU core with 128b multimedia extensions,
10 floating-point multiplier accumulators, four floating-point dividers, an
MPEG2 decoder, a 10-channel DMA controller, and other peripherals with 128b
internal buses on one die. It contains 10.5M transistors in
17x14.1mm2 and dissipates 15W at 1.8V
| 15.2 | A High-Bandwidth Superscalar Microprocessor for Multimedia Applications | 2:00 PM |
M. Raam, R. Agarwal, K. Malik, H. Landman, H. Tago, T. Teruyama, T.
Sakamoto, T. Yoshida1, S. Yoshioka1, Y.
Fujimoto1, T. Kobayashi1, T. Hiroi2, M.
Oka2, A. Ohba2, M. Suzuoki2, T.
Yutaka2, Y. Yamamoto2
Toshiba Corp., San Jose, CA, / 1Kawasaki, Japan
2Sony
Computer Entertainment, Inc., Tokyo, Japan
A 250MHz 2-way superscalar MIPS-compatible microprocessor for multimedia and
networking applications with internal 8kB D-cache, 16kB
I-cache, 1kx128b scratch-pad RAM tightly coupled to the pipe and 128b internal
datapaths. >100 multimedia instructions are extended on a
10.9x6.3mm2 die in 0.18µm CMOS at 1.8V
| 15.3 | A 2.5GFLOPS 6.5M Polygons/s 4-Way VLIW Geometry Processor with SIMD Instructions & Software Bypass | 2:30 PM |
N. Higaki, H. Kubosawa, S. Ando, H. Takahashi, Y. Asada,
H. Anbutsu, T. Sato, M. Sakate, A. Suga, M. Kimura, H. Miyake,
H. Okano, A. Asato, Y. Kimura, H. Nakayama, M. Kimoto1, K.
Hirochi1, H. Saito1, N. Kaido1, Y.
Nakagawa1, T. Shimada1
Fujitsu Labs., Ltd., Kawasaki, Japan
1 Fujitsu, Ltd., Kawasaki,
Japan
A 312MHz 2.5GFLOPS 4-way VLIW geometry processor with an on-chip 66MHz PCI/AGP
bus bridge provides 6.5Mp/s on a 9.18x9.11mm2 die in 0.21µm
2.5V three-layer-metal CMOS dissipating 7.5W. SIMD instructions and a software
bypass mechanism are used.
| BREAK | 3:00 PM |
| 15.4 | A 32b 64-Matrix Parallel CMOS Processor | 3:15 PM |
S. Pan, Y. Ben-Arie, E. Orian, I. Barak, Y. Shapira, S. Bresticker,
H. David, H. Folkman, J. Efrat, L. Tzukerman, Z. Dahan, D. Kolton
Motorola, Inc., Schaumburg, IL
This 32b floating-point 0.35µm CMOS processor with 64-matrix parallel
computing units uses logarithm-domain nonlinear computing and SIMD/VLIW
architecture to sustain 10GFLOPS on matrix multiply, FIR filter-bank, and
nonlinear polynomials. It can be either a coprocessor or a stand-alone DSP chip
with <3W at 120MHz and 3.3V.
| 15.5 | A Fully-Parallel 1Mb CAM LSI for Real-Time Pixel-Parallel Image Processing | 3:45 PM |
T. Ikenaga, T. Ogura
NTT Labs, Kanagawa, Japan
A 3 to 640GOPS CAM for 128x128 pixel-parallel image processing combines 1-D
(intra-block) and 2-D (inter-block) structure with word-parallel associative
and data-transfer functions. The 15.5M-transistor 16.1x17.0mm2 die
in 0.25µm CMOS dissipates 2.3W at 40MHz at 2.5V.
| 15.6 | A Single-Chip MPEG-2 Video Audio and System Encoder | 4:15 PM |
G. Kizhepat, K. Choy, R. Hinchley, P. Lowe, R. Yip
iCompression, Inc., Santa Clara, CA
A 6.1M-transistor 0.35µm CMOS 90MHz 3.3V 13.1x13.1mm2chip
MPEG-2 MP@ML video, audio and system encoder integrates two DSPs, video filter,
video encoding engine, two memory interfaces, and system multiplexer. Flexible
system interfaces support PCI, ROM, and external host.
| 15.7 | A Single-Chip CIF 30Hz H.261, H.263, and H.263+ Video Encoder/Decoder with Embedded Display Controller | 4:45 PM |
M. Harrand, J. Sanches, A. Bellon, J. Bulone, A. Tournier, O. Deygas, J.-C.
Herluison, D. Doise, E. Berrebi
STMicroelectronics, Crolles, France
A single-chip video CODEC with embedded display controller simultaneously
encodes and decodes up to 30 CIF pictures per second according to
video-teleconferencing recommendations H261, H263 and H263+. The
132mm2 0.35µm 5-level CMOS chip consumes 1.4W at 54MHz.
Emphasis is on hardware/software partitioning and co-design.
| 15.8 | Flip-Flop SelectionTechnique for Power-Delay Trade-off | 5:15 PM |
M. Hamada, T. Terazawa1, T. Higashi1, S.
Kitabayashi1, S. Mita,
Y. Watanabe1, M. Ashino, H. Hara, T. Kuroda
Toshiba Corp./1Toshiba Micro Electronics Corp., Kawasaki, Japan
Three discrete cosine transform block types in conventional design (Conv-DCT),
0.88mW/MHz design (LP-DCT), and 9.99ns design (HS-DCT) use 0.3µm CMOS.
LP-DCT consumes 24%-51% less power without speed degradation, and HS-DCT
operates 25% faster than Conv-DCT.
| CONCLUSION | 5:30 PM |
Chair: G. Gerosa, Motorola Inc., Austin, TX
Assoc. Chair: M. Leary, Chromatic Research, Sunnyvale, CA
| 16.1 | A 1.9V I/O Buffer with Gate-Oxide Protection and Dynamic Bus Termination for 400MHz Sparc Microprocessor | 1:30 PM |
G. Singh, R. Salem
Sun Microsystems, Inc., Palo Alto, CA
A 1.9V buffer using 0.21µm CMOS uses circuit techniques to restrict
gate-stress on all MOS elements below 2.2V, the maximum allowed by the process
technology, without compromising speed and layout area. The circuit provides
dynamic bus termination.
| 16.2 | A Versatile 3.3V/2.5V/1.8V CMOS I/O Driver | 2:00 PM |
H. Sanchez, J. Siegel, C. Nicoletta, J. Alvarez, J. Nissen, G. Gerosa
Motorola Somerset Design Center, Austin, TX
An I/O driver supports 3.3V/2.5V/1.8V interfaces with a 3.5nm Tox
1.8V 0.2µm CMOS technology. A bias generator, its switch-capacitors, and a
protection network guarantee reliability and improve noise rejection. Measured
output timing degradation is 2.5ps per number of I/Os switching. Buried
resistors control output impedance. 2ns interface delay with worst-case I/O
switching allows 400MHz operation.
| 16.3 | A CMOS Interface Circuit for Detection of 1.2Gb/s RZ Data | 2:30 PM |
J. Savoj, B. Razavi
University of California, Los Angeles, CA
A CMOS interface circuit incorporates an amplifier with 2GHz bandwidth,
interleaved matching filters, and a 1:2 demultiplexer. Fabricated in 0.6µm
CMOS, the interface achieves 2mVpp sensitivity while consuming 142mW
from a 3.3V supply, and occupying 575x1323µm2.
| BREAK | 3:00 PM |
| 16.4 | A 18µA Standby-Current 1.8V 200MHz Microprocessor with Self Substrate-Biased Data Retention Mode | 3:15 PM |
H. Mizuno, K. Ishibashi, T. Shimura, T.Hattori, S. Narita,
K. Shiozawa, S. Ikeda, K. Uchiyama
Hitachi Ltd., Tokyo, Japan
A 1.8V 200MHz microprocessor in 0.2µm CMOS uses a switched
substrate-impedance scheme to bias substrates in standby mode while maintaining
a 200MHz operating speed. It also offers a battery-backup capability in a self
substrate-biased data retention mode, in which it consumes only 17.8µA.
| 16.5 | Sense Amplifier-Based Flip-Flop | 3:45 PM |
B. Nikolic1,2, V. Stojanovic3, V.
Oklobdzija4, W. Jia1, J. Chiu1,
M. Leung1
1Texas Instruments, San Jose, CA
2University of
California, Davis, CA
3Stanford University, Stanford,
CA
4Integration, Berkeley, CA
A sense-amplifier-based flip-flop with improved second stage has balanced
differential output and improved drive ability, setup time, and delay. The test
chip in Leff=0.18µm CMOS exhibits 210psTDQ and
230psTCQ delay with 200fF output loading.
| 16.6 | Asynchronous Sense Differential Logic | 4:15 PM |
B.-S. Kong, J.-D. Im, Y.-C. Kim, S.-J. Jang, Y.-H. Jun
LG Semicon, Seoul, Korea
An asynchronous sense differential logic family employing self-timing for speed
enhancement, and charge-recycling for power efficiency, is up to 49% faster
than other types of dynamic logic. A 0.97ns 64b adder in 0.35µm 2.5V
process using this circuit technique has power comparable to that of
conventional dynamic circuits.
| 16.7 | Low-Power Design of High-Capacitive CMOS Circuits Using a Charge Sharing Scheme | 4:45 PM |
M. Khellah, M. Elmasry
University of Waterloo, Ontario, Canada
A 256x256 ROM, a 2b 2.6mm internal bus, and a 32x32b translation look-aside
buffer (TLB) in 0.6µm CMOS use a low-swing approach based on charge
sharing. Measurements of the ROM and bus chips show 2.5 to 5.5ns delay for 3.3
to 2.0V supply. The chips operate to 1.2V.
| CONCLUSION | 5:15 PM |