| SESSION MA 1 | PLENARY SESSION - INVITED ADDRESSES |
| 1.1 | The New Frontier Created by High-Bandwidth Digital Video Systems and Services |
| 1.2 | Is High-Speed the Only Solution to Exploit the Intrinsic Computational Power of Silicon? |
| 1.3 | Broadband Communications ICs: Enabling High- Bandwidth Connectivity in the Home and Office |
| SESSION MP 2 | DISK-DRIVE SIGNAL PROCESSING |
| 2.1 | A 450Mb/s Analog Front-End for PRML Read Channels |
| 2.2 | A Trellis-Coded E 2 PRML Digital Read/Write Channel IC |
| 2.3 | A Mixed-Signal 120MSample/s PRML Solution for DVD Systems |
| 2.4 | A 360Mb/s (400MHz) 1.1W 0.35µm CMOS PR4/EPR4 Read Channel with 6 Burst 8-20x Oversampling Digital Servo |
| 2.5 | 260Mb/s Mixed-Signal Single-Chip Integrated System Electronics for Magnetic Hard Disk Drives |
| 2.6 | A 3V 10-100MHz Continuous-Time Seventh-Order 0.05 o Equiripple Linear-Phase Filter |
| 2.7 | A 300Mb/s BiCMOS Disk-Drive Channel with AdaptiveAnalog Equalizer |
| SESSION MP 3 | OVERSAMPLED MODULATORS |
| 3.1 | A 1.5V 1.0mW Audio [Sigma][Delta] Modulator with 98dB Dynamic Range |
| 3.2 | A 1.8mW CMOS [Sigma][Delta] Modulator with Integrated Mixer for A/D Conversion of IF Signals |
| 3.3 | A Nyquist-Rate Pipelined Oversampling A/D Converter |
| 3.4 | A Sixth-Order Continuous-Time Bandpass [Sigma][Delta] Modulator for Digital Radio IF |
| 3.5 | A Bandpass Mismatch-Shaped Multibit [Sigma][Delta] Switched- Capacitor DAC Using Butterfly Shuffler |
| 3.6 | A 100MHz IF, 400MSample/s CMOS Direct-Conversion Bandpass [Sigma][Delta] Modulator |
| 3.7 | A 400MHz 12b 18mW IF Digitizer with Mixer Inside a [Sigma][Delta] Modulator Loop |
| SESSION MP 4 | RF AND ANALOG TECHNOLOGIES |
| 4.1 | How SiGe Evolved Into a Manufacturable Semiconductor Production Process |
| 4.2 | A DECT Transceiver Chip Set Using SiGe Technology |
| 4.3 | Monolithic CMOS Distributed Amplifier and Oscillator |
| 4.4 | Fully-Integrated CMOS RF Amplifiers |
| 4.5 | High-Frequency Analog Filters in Deep-Submicron CMOS Technology |
| 4.6 | Analog Broadband Communication Circuits in Pure Digital Deep-Sub-Micron CMOS |
| 4.7 | Tunable, Switchable, High-Q VHF Microelectromechanical Bandpass Filters |
| 4.8 | A 1.9GHz Micromachined-Based 126dBc/Hz CMOS VCO |
| 4.9 | An Analog CMOS IC for Template Matching |
| SESSION MP 5 | MICROPROCESSORS |
| 5.1 | A 500MHz 64b RISC CPU with 1.5MB On-Chip Cache |
| 5.2 | 600MHz G5 S/390 Microprocessor |
| 5.3 | Storage Hierarchy to Support a 600MHz G5 S/390 Microprocessor |
| 5.4 | A 7th-Generation x86 Microprocessor |
| 5.5 | An Out-of-Order Three-Way Superscalar Multimedia h5 Floating-Point Unit |
| 5.6 | A 450MHz PowerPC TM Microprocessor with Enhanced Instruction Set and Copper Interconnect |
| 5.7 | A 600MHz IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video |
| SESSION MP 6 | FLASH AND FERRO MEMORY |
| 6.1 | A Sub-40ns Random-Access Chain-FRAM Architecture with 7ns Cell-Plate-Line Drive |
| 6.2 | A 0.5µm 3V 1T1C 1Mb FRAM with a Variable Reference Bitline Voltage Scheme Using a Fatigue-Free Reference Capacitor |
| 6.3 | Multi-Level Technologies for FRAM Embedded Reconfigurable Hardware |
| 6.4 | Multi-Phase Driven Split Word-Line-Ferroelectric Memory Without Plate Line |
| 6.5 | A 256Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Application |
| 6.6 | A 130mm 2 256Mb NAND Flash with Shallow Trench Isolation Technology |
| 6.7 | A 29mm 2 1.8V-Only 16Mb DINOR Flash Memory with Gate-Protected Poly-Diode Charge Pump |
| 6.8 | A 3.3V 90MHz Flash Memory Module Embedded in a 32b RISC Microcontroller |
| SESSION TA 7 | MEMS, ICS, AND MICROSYSTEMS |
| 7.1 | 2D Magnetic Micro-Fluxgate System with Digital Signal Output |
| 7.2 | An Interface IC for Capacitive Silicon µg Accelerometer |
| 7.3 | An SOI, 0.6mV Offset, Temperature-Compensated Hall Sensor Readout IC for Automotive Applications up to 200 o C |
| 7.4 | A Programmable Mixed-Voltage Bus Interface and Sensor Readout with Built-In Self-Test |
| 7.5 | A 15x15mm 2 Single-Chip Fingerprint Sensor and Identifier Using Pixel-Parallel Processing |
| 7.6 | A CMOS Micro Touch Pad |
| 7.7 | A 100Frames/s CMOS Active Pixel Sensor for 3D-Gesture Recognition System |
| SESSION TA 8 | ANALOG TECHNIQUES I |
| 8.1 | A 14b 150MSample/s Update Rate Q 2 Random Walk CMOS DAC |
| 8.2 | A 14b 100MSample/s CMOS DAC Designed for Spectral Performance |
| 8.3 | A 110dB THD, 18mW DAC Using Output Sampling and Feedback to Reduce Distortion |
| 8.4 | A Multi-bit [Sigma][Delta] Audio DAC with 120dB Dynamic Range |
| 8.5 | PowerDAC: A Single-Chip Audio DAC with 70%-Efficient Power Stage in 0.5µm CMOS |
| 8.6 | A DC/DC Converter Using Divided Switches with Current Control Technique |
| 8.7 | Damping Factor Control Frequency Compensation Technique for 2V Low-Power Large- Capacitative-Load Applications |
| SESSION TA 9 | COMMUNICATIONS TECHNIQUES AND ATM |
| 9.1 | A 13.56MHz CMOS RF Identification Transponder IC with Dedicated CPU |
| 9.2 | A CMOS Dual Channel 100MHz-1.1GHz Transmitter for Cable Applications |
| 9.3 | A BiCMOS 300ns Attack-Time AGC Amplifier with Peak-Detect and Hold for High-Speed Wireless ATM Systems |
| 9.4 | A 622Mb/s CMOS ATM Switch Access LSI with Maintenance Cycle Interleaved Pipeline Architecture |
| 9.5 | A 622Mb/s 256k ATM Resource-Management Circuit |
| 9.6 | A 10Gb/s (1.25Gb/sx8) 2x4 CMOS/SIMOX ATM Switch |
| SESSION TA 10 | CLOCKING AND SYNCHRONIZATION |
| 10.1 | 110GB/s Simultaneous Bi-Directional Transceiver Logic Synchronized with a System Clock |
| 10.2 | A 750Mb/s 0.6µm CMOS Two-Phase Input Port Using Self-Tested Self-Synchronization |
| 10.3 | A 2B Parallel 1.25Gb/s Interconnect I/O Interface with Self-Configurable Link and Plesiochronous Clocking |
| 10.4 | Low-Skew Clock Generator with Dynamic Impedance and Delay Matching |
| 10.5 | Dual-Loop Spread-Spectrum Clock Generator |
| 10.6 | Clock Dithering for Electromagnetic Compliance Using Spread-Spectrum Phase Modulation |
| SESSION TA 11 | HIGH SPEED SRAM |
| 11.1 | A 1.4ns Access 700MHz 288kb SRAM Macro with Expandable Architecture |
| 11.2 | A 500MHz 1.5MB Cache with On-Chip CPU |
| 11.3 | A 0.18ns 32-Wordx32b Three-Port Bipolar Register File Implemented Using a SiGe HBT BiCMOS Technology |
| 11.4 | A 500MHz Pipelined Burst SRAM with Improved SER Immunity |
| 11.5 | A 940MHz Data Rate 8Mb CMOS SRAM |
| 11.6 | An 18Mb, 12.3GB/s CMOS Pipeline-Burst Cache SRAM with 1.54Gb/s/pin. |
| SESSION TP 12 | TECHNOLOGY DIRECTIONS: EMERGING MICROSYSTEMS FOR PORTABLE APPLICATIONS |
| 12.1 | 10mW CMOS Sensor and Classifier for Handheld 1000 Image/s Optical Character-Recognition |
| 12.2 | A CMOS Vision Chip with SIMD Processing-Element h5 Array for 1ms Image Processing |
| 12.3 | On-Chip Integrated CMOS Optical Microspectrometer with Light-to-Frequency Converter and Bus Interface |
| 12.4 | Electronics of Single-Wall Carbon Nanotubes |
| 12.5 | A 160x120 Pixel Liquid-Crystal-on-Silicon Microdisplay with an Adiabatic DAC |
| 12.6 | A Wireless Single-Chip Telemetry-Powered Neural-Stimulation System |
| 12.7 | An Implantable Neuro-Stimulator Device for a Retinal Prothesis |
| SESSION TP 13 | WIRELESS CIRCUITS |
| 13.1 | A Wide-Band Direct Conversion Receiver for WCDMA Applications |
| 13.2 | A 22mW NADC Receiver IF Chip with Integrated Second IF Channel Filtering |
| 13.3 | Dual-Band High-Linearity Variable-Gain Low-Noise Amplifiers for Wireless Applications |
| 13.4 | 2.1GHz Direct-Conversion GaAs Quadrature Modulator IC for W-CDMA Base Station |
| 13.5 | A Single-Chip CMOS Direct-Conversion Transceiver for 900MHz Spread-Spectrum Digital Cordless Phones |
| 13.6 | A Monolithic 3.7W Silicon Power Amplifier with 59% PAE at 0.9GHz |
| 13.7 | A 20mA-Receive, 55mA-Transmit, Single-Chip GSM Transceiver in 0.25µm CMOS |
| 13.8 | A 1.8V 14b Audio Front-End Codec for Digital Cellular Phones |
| SESSION TP 14 | XDSL SIGNAL PROCESSORS |
| 14.1 | A 0.5µm CMOS ADSL Analog Front-End IC |
| 14.2 | A CMOS Analog Front-End IC for DMT ADSL |
| 14.3 | CODEC for Echo-Cancelling Full-Rate ADSL Modems |
| 14.4 | A 25kft 768kb/s CMOS Transceiver for Multiple Bit-Rate DSL |
| 14.5 | An Integrated Analog Front-End for VDSL |
| 14.6 | A 70Mb/s Variable-Rate DMT-Based Modem for VDSL |
| 14.7 | A 52Mb/s Universal DSL Transceiver IC |
| 14.8 | An Integrated Adaptive Analog Balancing Hybrid for (A)DSL Modems |
| SESSION TP 15 | MULTIMEDIA PROCESSORS |
| 15.1 | A Microprocessor with 128b CPU, 10 Floating-Point MACs, 4 Floating-Point Dividers, and MPEG2 Decoder |
| 15.2 | A High-Bandwidth Superscalar Microprocessor for Multimedia Applications |
| 15.3 | A 2.5GFLOPS 6.5M Polygons/s 4-Way VLIW Geometry Processor with SIMD Instructions & Software Bypass |
| 15.4 | A 32b 64-Matrix Parallel CMOS Processor |
| 15.5 | A Fully-Parallel 1Mb CAM LSI for Real-Time Pixel-Parallel Image Processing |
| 15.6 | A Single-Chip MPEG-2 Video Audio and System Encoder |
| 15.7 | A Single-Chip CIF 30Hz H.261, H.263, and H.263+ Video Encoder/Decoder with Embedded Display Controller |
| 15.8 | Flip-Flop SelectionTechnique for Power-Delay Trade-off |
| SESSION TP 16 | DIGITAL CIRCUIT TECHNIQUES |
| 16.1 | A 1.9V I/O Buffer with Gate-Oxide Protection and Dynamic Bus Termination for 400MHz Sparc Microprocessor |
| 16.2 | A Versatile 3.3V/2.5V/1.8V CMOS I/O Driver |
| 16.3 | A CMOS Interface Circuit for Detection of 1.2Gb/s RZ Data |
| 16.4 | A 18µA Standby-Current 1.8V 200MHz Microprocessor with Self Substrate-Biased Data Retention Mode |
| 16.5 | Sense Amplifier-Based Flip-Flop |
| 16.6 | Asynchronous Sense Differential Logic |
| 16.7 | Low-Power Design of High-Capacitive CMOS Circuits Using a Charge Sharing Scheme |
| SESSION WA 17 | IMAGE SENSORS AND INTEGRATED SYSTEMS |
| 17.1 | A 1/2-Inch 1.3M-Pixel Progressive Scan CCD Image Sensor Employing 0.25µm Gap Single-Layer Poly-Si Electrodes |
| 17.2 | A 1/4-inch 630k-pixel IT-CCD Image Sensor with High-Speed Capture Capability |
| 17.3 | An Integrated 800x600 CMOS Imaging System |
| 17.4 | Single-Chip Video Camera with Integrated Functions, with Digital FPN, Defective-Pixel, and Gamma Correction |
| 17.5 | A 604x512 CMOS Image Sensor with Ultra Wide Dynamic Range Floating-Point Pixel-Level ADC |
| 17.6 | A Locally Adaptive CMOS Image Sensor with 90dB Dynamic Range |
| 17.7 | A 250mW, 60Frames/s, 1280x720 Pixel, 9b CMOS Digital Image Sensor |
| SESSION WA 18 | NYQUIST ADCS |
| 18.1 | A 12b Digital-Background-Calibrated Algorithmic ADC with -90dB THD |
| 18.2 | A 3.3V 10b 25MSample/s Two-Step ADC in 0.35µm CMOS |
| 18.3 | A 65mW 10b 40MSample/s BiCMOS Nyquist ADC in 0.8mm 2 |
| 18.4 | A 75mW 10b 20MSample/S CMOS Subranging ADC with 59dB SNDR |
| 18.5 | A CMOS 6b 500MSample/s ADC for Hard Disk Drive Read Channel |
| 18.6 | A 6b 500MSample/s CMOS Flash ADC with Background Interpolated Auto-Zeroing Technique |
| 18.7 | Feedback Charge-Transfer Latch Comparator with Zero Static Power |
| SESSION WA 19 | TRANSCEIVER DSPS |
| 19.1 | A Single-Chip Universal Digital Satellite Receiver with 480MHz IF Input |
| 19.2 | A Single-Chip Universal Cable Set-Top Box/Modem Transceiver |
| 19.3 | A Digital Television Demodulator IC with 256 Tap Equalizer |
| 19.4 | A 4-Channel Diversity QAM Receiver for Broadband Wireless Communications |
| 19.5 | An All-Digital IF GPS Synchronizer for Portable Applications |
| 19.6 | A 755Mb/s Viterbi Decoder for the RM (64,35,8) Subcode |
| SESSION WA 20 | CLOCK AND DATA RECOVERY |
| 20.1 | A 250MHz Low-Jitter Adaptive Bandwidth PLL |
| 20.2 | A 0.155, 0.622, and 2.488Gb/s Automatic Bit Rate Selecting Clock and Data Recovery IC for Bit Rate Transparent SDH-Systems |
| 20.3 | An Auto-Ranging 50-210Mb/s Clock Recovery Circuit with a Time-to-Digital Converter |
| 20.4 | A 0.5-3.5Gb/s Low-Power Low-Jitter Serial Data CMOS Transceiver |
| 20.5 | A 1Gb/s CMOS Clock and Data Recovery Circuit |
| 20.6 | A 2-1600MHz 1.2-2.5V Clock-Recovery PLL with Feedback Phase Selection and Averaging Phase Interpolation for Jitter Reduction |
| SESSION WA 21 | TECHNOLOGY DIRECTIONS: DIGITAL TECHNOLOGIES |
| 21.1 | Experiences of IP Reuse in System-on-Chip Design for ADSL |
| 21.2 | Trends Toward Spatial Computing Architectures |
| 21.3 | A Dynamically Reconfigurable Logic Engine with a Multi-Context/Multi-Mode Unified-Cell Architecture |
| 21.4 | The Impact of Technology Evolution and Scaling on Electrostatic Discharge (ESD) Protection in High-Pin-Count High-Performance Microprocessors |
| 21.5 | A Fault-Detecting 400MHz Floating-Point Unit for a Massively-Parallel Computer |
| 21.6 | Access Optimizer to Overcome the "Future Walls of Embedded DRAMs" in the Era of Systems on Silicon |
| 21.7 | Picosecond Imaging Circuit Analysis of the Power3 Clock Distribution |
| SESSION WP 22 | OPTICAL LINKS |
| 22.1 | Si Bipolar 3.3V Transmitter/Receiver IC Chip Set for 1Gb/s 12-Channel Parallel Optical Interconnects |
| 22.2 | A 12-Channel Data-Format-Free 1Gb/s/ch Parallel Optical Receiver |
| 22.3 | A SiGe Single-Chip 3.3V Receiver IC for 10Gb/s Optical Communication Systems |
| 22.4 | A 60dB Gain 55dB Dynamic Range 10Gb/s Broadband SiGe HBT Limiting Amplifier |
| 22.5 | High-Bandwidth BiCMOS OEIC for Optical Storage Systems |
| 22.6 | 15mW 155Mb/s CMOS Burst-Mode Laser Driver with Automatic Power Control and End-of-Life Detection |
| 22.7 | Optical Transceiver Formed with Fiber-Embedded Lightwave Circuit on Silicon Substrate |
| SESSION WP 23 | ANALOG TECHNIQUES II |
| 23.1 | A 450kHz CMOS Gm-C Bandpass Filter with 0.5% Center Frequency Accuracy for On-Chip PDC IF Receivers |
| 23.2 | A 2.5V 30-100MHz 7th-Order Equiripple Group-Delay Continuous-Time Filter and Variable-Gain Amplifier Implemented in 0.25µm CMOS |
| 23.3 | A 2.5Gb/s Adaptive Cable Equalizer |
| 23.4 | A 13mW 500kHz Data-Acquisiton IC with 4.5 Digit DC and 0.02% Accurate True-RMS Extraction |
| 23.5 | A 200MSample/s 10mW Switched-Capacitor Filter in 0.5µm CMOS Technology |
| 23.6 | A 2.6GHz/5.2GHz CMOS Voltage-Controlled Oscillator |
| 23.7 | A 6.5GHz Monolithic CMOS Voltage-Controlled Oscillator |
| 23.8 | A 9.8GHz Back-Gate Tuned VCO in 0.35µm CMOS |
| SESSION WP 24 | DRAM |
| 24.1 | A 1.6GB/s DRAM with Flexible Mapping Redundancy Technique and Additional Refresh Scheme |
| 24.2 | A 2.5V 333Mb/s/pin 1Gb Double Data Rate SDRAM |
| 24.3 | An 800MB/s 72Mb SLDRAM with Digitally-Calibrated DLL |
| 24.4 | 64Mb 6.8ns Random ROW Access DRAM Macro for ASICs |
| 24.5 | A 250Mb/s/pin, 1Gb Double-Data-Rate SDRAM with Bidirectional Delay and Inter-Bank Shared Redundancy Scheme |
| 24.6 | A 12ns 8MB DRAM Secondary Cache for a 64b Microprocessor |
| 24.7 | A 390mm 2 16-bank 1Gb DDR SDRAM with Hybrid Bitline Architecture |
| SESSION WP 25 | DIGITAL/TECHNOLOGY DIRECTIONS JOINT SESSION: SOI MICROPROCESSORS AND MEMORY |
| 25.1 | Non-Fully-Depleted SOI Technology for Digital Logic |
| 25.2 | CMOS/SOI Technology Performance and Modelling |
| 25.3 | A 580MHz 32b PowerPC Microprocessor in 0.12µm L eff /b br CMOS SOI with Cu Interconnects |
| 25.4 | A 0.25µm 600MHz 1.5V SOI 64-Bit ALPHA TM Microprocessor |
| 25.5 | Performance Characteristics of SOI DRAM for Low-Power Application |
| 25.6 | A 0.25µm 1.8V 1GHz PLL for SOI Microprocessors |
| 25.7 | A 0.20µm 1.8V SOI 550MHz 64b PowerPC Microprocessor with Cu Interconnects |