The tutorials introduce non-experts to the state-of-the-art in integrated circuits, and give understanding of and perspective on presentations at ISSCC. Each tutorial is on a seminal topic related to the conference and is presented by an expert member of the Technical Program Committee. The 6 tutorials run in parallel on February 14 and are scheduled to begin at 8 AM, 10 AM, and 3 PM. Each is about 90 minutes. Attendees may register for up to 3 tutorials, on a first-come, first-served basis. Attendees will be informed as to the time of their sessions. A ticket, required for admission to each tutorial, will be included in the ISSCC registration packet.
Registration: Use the registration form on Advance Program centerfold.
Design Methodologies for Interconnect in GHz+ ICs
Specific impacts of interconnect RLC effects on digital IC design in the
GigaHertz domain. Key analysis methods and tools, including R and 3D
capacitance extraction and inductance analysis with emphasis on practical rules
of thumb. Circuit solutions for mitigating the growing interconnect penalty,
including repeaters, coupling noise management, wire/FET tradeoffsand
signalling methods. Impact of the interconnect penalty on chip partioning and
micro-architecture.
Instructor: Samuel Naffziger, HP Engineer/Scientist, Fort Collins, CO, received BSEE from the California Institute of Technology in 1988 and MSEE from Stanford in 1993. He has been a technical lead in circuit design on several microprocessors since 1990. Interests include general high-speed circuit techniques, arithmetic circuits, clocking, latching, I/Os, memories, and interconnect design. He holds 8 patents in circuits and micro-architecture.
Residential High-Bandwidth Access Technology
Competing technologies are emerging to provide high-speed Internet access to
the residential consumer. This tutorial provides a high-level overview of
several of these technologies including cable, twisted pair (xDSL), wireless,
and power-line modem access. A system-level explanation of each approach and a
discussion of advantages and potential pitfalls of each technology are
presented.
Instructor: Trudy Stetzler, Texas Instruments, Houston, TX received BSEE in 1984 from Pennsylvania State Univ. and MSEE from UC Berkeley in 1985. She joined Bell Labs in 1985 designing analog and RF ICs for wired and cellular phones. She was elected Distinguished Member of Technical Staff in 1995. In 1997 she received MBA from Wharton School and joined TI. She is Senior Member of Technical Staff analyzing communications systems.
High-Speed CMOS ADCs
50-400MHz 4-10b CMOS ADCs for embedded applications, dealing mainly with flash
architectures with and without folding. Comparators and pre-amps are discussed.
Averaging is used to improve accuracy without increased circuit complexity.
After attaining a level of performance, interpolation and folding are used to
reduce component count without loss of performance. A design example is given.
Measured and published results are compared.
Instructor: Klaas Bult, Broadcom Corp., Irvine, CA, received MSEE (1986) and PhD (1988) from University of Twente, Enschede, The Netherlands. In 1988 he joined Philips Research Labs, working on analog CMOS circuits, for consumer applications in audio and video. In 1993, he became part-time professor at University of Twente. In 1994, he became Assoc. Prof. at UCLA. In 1996, he joined Broadcom as Director of Analog and RF Microelectronics Technology. His work focusses on high-speed CMOS analog and mixed-signal processing.
Video Compression Circuits
An introduction to circuits for MPEG encoding/decoding: discrete cosine
transform, motion compensation, quantization, entropy coding, bitstream
packing/unpacking. Circuits for alternative coding schemes: wavelet/subband
filterbanks. High speed and low power implementations.
Instructor: Stephen Molloy, Luxxon Corp., San Jose, CA, received the BSEE from Rensselaer Polytechnic Institute in 1991, and the MS and PhD in EE from UCLA in 1993 and 1997. At UCLA his research interests included video compression circuits, video signal processors, and low-power design. He currently designs low-power, high-performance digital camera ICs.
Single-Chip CMOS Imaging System
Overview of single-chip CMOS imaging systems, from fabrication technology to
pixel and system architecture. The tutorial follows the signal path of a
single-chip CMOS imaging system, photon conversion to voltage, pixel
architectures, sensor performance measures, A/D conversion, color processing,
and on-chip image processing, and impact of CMOS device and technology scaling
on CMOS image sensor performance. R&D trends are summarized.
Instructor: Hon-Sum Philip Wong, received PhD EE from Lehigh Univ., Bethlehem, PA, and joined the IBM T. J. Watson Research Center, Yorktown Heights in 1988. To 1992, he worked on a high-resolution, high-color-fidelity CCD image scanner for art work archiving. Since 1993, he worked on devices, processes, and applications for sub-50nm CMOS. He is on ISSCC and IEDM program committees.
Instructor: Abbas El Gamal, in 1978 received a PhD EE from Stanford, where he is an Assoc. Prof. of EE. From 1978-80 he was Asst. Prof. of EE at USC. From 84-88, he was Director of LSI Logic Research Lab, where he developed compilation technology and DSP and image processing ASICs, and then cofounder and Chief Scientist of Actel. From 1990-1995 he was a cofounder and Chief Technical Officer of Silicon Architects.
Signaling in High-Performance Memory Systems
Transmission line characteristics, termination methods, noise sources and
coupling, signal levels, current-mode, voltage-mode, single-ended and
differential signaling, clocking, references. Characteristics of busses,
packaging considerations, limitations on bus signaling speed. Bus-based memory
signaling, including RDRAM, SLDRAM, DDR, PC100. Improving memory signaling.
Instructor: John Poulton, Research Prof., Dept. of Computer Science, Univ. of North Carolina at Chapel Hill, received BS from Virginia Tech (1967), MS from SUNY-Stony Brook (1969), and PhD from UNC-Chapel Hill (1980), all in Physics. Since 1980, he has designed experimental computer graphics systems at UNC-CH. His research interests include logic-enhanced memory systems, high-performance signaling, and architectures for graphics and imaging.