| FORMAL OPENING OF CONFERENCE | 8:30 AM |
| 1.1 | The New Frontier Created by High-Bandwidth Digital Video Systems and Services | 8:45 AM |
Haruo Nakatsuka, Toshiba Corp., Kawasaki, Japan
Digital video systems have been motivated by the needs of high-quality
pictures. In the future, however, they will play more important roles in
digital home electronics with much more sophisticated services backed up by
advanced high-bandwidth technology.
Passive data services, such as HDTV, are the present focus of the digital
broadcast business. This type of application is met by MPEG2 encoding/decoding
implemented by current LSI technology. More sophisticated applications such as
interactive TV, with 3D capability and intelligent data handling at the viewer
site, require LSIs with higher bandwidth. A 100M polygon/s processor and
40GB/s memory at the viewer site enables services such as TV-linked games,
virtual shopping malls, and 3D cartoons without overloading the transmission
medium. Mixed-reality image processing with smooth fusion of live moving image
data and cartoon graphics requires sophisticated 3D modeling technology.
Another high-bandwidth application is real-time video-image indexing and
filtering for the home server. To recognize and set the index to the live
image data requires DSPs that are 102 to 103 times
faster.
| ISSCC, SSCS, JSSC, and IEEE AWARD PRESENTATIONS | 9:35 AM |
| BREAK | 10:00 AM |
| 1.2 | Is High-Speed the Only Solution to Exploit the Intrinsic Computational Power of Silicon? | 10:15 AM |
Dr. Theo Claasen,
Philips Semiconductors B.V., Eindoven, The Netherlands
The progression of silicon technology has resulted in the emergence of
computation-intensive digital systems that in turn challenge the progression in
technology. Computational intensity eventually is the main reason for
unsatisfiable demand for bandwidth. The computational power of silicon usually
is exploited by increase of synchronous digital circuitry clock speed. What is
the intrinsic computational power of silicon and how can it be exploited? This
raises questions of the effects of speed on power dissipation and suggests
alternatives to brute compute power through architectures exploiting
concurrency, be it parallelism or serialism (pipelining). Flexibility issues
such as architectural reconfigurability and programability are also involved.
In this spectrum of architectures, software and "software-friendliness" will be
addressed from the points of view of CPU, DSPs and mediaprocessors. Such
devices are key to system solutions targeted at a wide range of applications.
The introduction of the Silicon System Platform concept places these key
components in perspective and shows how an heterogeneous composition in an
overall communication structure may be the solution for systems-on-a-chip
allowing maximum reuse of hardware and software. The concepts will be
illustrated by examples from relevant application areas such as interactive
digital TV, optical storage, set-top-boxes and handheld communication systems.
Process technology and manufacturing technology will advance to provide these
capabilities cost-effectively in products for the end-customer.
| 1.3 | Broadband Communications ICs: Enabling High- Bandwidth Connectivity in the Home and Office | 11:05 AM |
Dr. Henry Samueli, Broadcom Corporation, Irvine, CA
The broadband revolution is here. High-bandwidth connectivity will
dramatically change the modes of life and work. Within the home, broadband
services are driven by both the television set and the personal computer.
Availability of digital programming content transforms the television set from
a broadcast-only to a fully interactive appliance. Availability of
multimedia-rich data services on the Internet drives the demand for
high-bandwidth remote-access PC connections via cable and xDSL modems. In the
office, there is also an ever-increasing need for high-bandwidth communications
to accommodate the explosive growth of network connections worldwide. Local
area network technologies such as Fast Ethernet and Gigabit Ethernet are being
developed to relieve these bandwidth bottlenecks.
Satisfying the need for these broadband services has required significant
advances in the levels of mixed-mode IC integration. Deep submicron
technologies have enabled cost-effective multi-million transistor ASICs with
multi-billion operations per second of signal processing capabilities that
would have occupied racks of hardware not that many years ago. As a result,
broadband digital communications is being transformed from specialized military
applications to commodity consumer products. This talk reviews current designs
and future design challenges for achieving the ambitious goal of universal
broadband connectivity.
| CONCLUSION | 12:00 NOON |
Chair: G. Uehara, University of Hawaii, Honolulu, HI
Assoc. Chair: K. Fukahori, Silicon Systems, Inc., San Jose, CA
| 2.1 | A 450Mb/s Analog Front-End for PRML Read Channels | 1:30 PM |
B.E. Bloodworth, P. Siniscalchi, G. De Veirman1, A. Jezdic,
R. Pierson, R. Sundararaman1
Texas Instruments, Dallas, TX
1Silicon Systems, Inc., Tustin,
CA
A 450Mb/s analog front-end for 16/17 code rate EPR4 read channel provides
constant-settling digital AGC, 20-120MHz equiripple linear-phase filtering with
active ac coupling, magnetoresistive asymmetry correction, and thermal asperity
compensation. The front-end occupies 2.3mm2 and dissipates 232mW.
| 2.2 | A Trellis-Coded E 2 PRML Digital Read/Write Channel IC | 2:00 PM |
T. Pan, S.-S. Lee, V. Balan, R. Gee, Y. Hsieh, P. Lai, A Liu, N. Rao,
R. Shenoy, T. Tham, D. Xu, A. Yeung, T. Zaheri, J. Fan, H. Gao,
J. Yang, Y. Wang, H. Thapar, M. Sugawara1, Y.
Tamura1
DataPath Systems, Inc., Los Gatos, CA
1NEC Electronics, Inc.,
Santa Clara, CA
A rate 8/9 Trellis-Coded E2PRML read/write channel IC achieves
>1.5dB SNR improvement over 16/17 EPRML at 2.8 user-bit density. The
0.29µm BiCMOS chip operates up to 400Mb/s with 1.1W read-mode power using
a single 3.3V supply. Die area is 13.5mm2.
| 2.3 | A Mixed-Signal 120MSample/s PRML Solution for DVD Systems | 2:30 PM |
R. Baird, P. Bhooma, G. Feyh, J. Graba, M. Hood, K. Kato, M. Kent, M.
Kostelnik, D. Kuai, K. Leung, Y. Lu, C. Painter, K. Patel,
D. Pietruszynski, P. Romano, C. Settje, Y.-S. Shaw, L. Supino,
M. Urabe, S. Zhu, C. Zook
Cirrus Logic, Austin, TX / Broomfield, CO / Fremont, CA / Tokyo, Japan
A 3.3V 120MSample/s fully-integrated DVD data channel, servo, and error
correction system uses 0.35µm CMOS technology and dissipates 1.5W. Six
[Delta][Sigma] converters are used in servo control loops. A 6b flash ADC,
digitally controlled VGAs, and digital equalization precede a modified Class I
partial-response system.
| BREAK | 3:00 PM |
| 2.4 | A 360Mb/s (400MHz) 1.1W 0.35µm CMOS PR4/EPR4 Read Channel with 6 Burst 8-20x Oversampling Digital Servo | 3:15 PM |
S. Sutardja
Marvell Semiconductor, Inc., Sunnyvale, CA
A 360Mb/s (400MHz) read channel targeting high-capacity, low-power disk drives
uses industry-standard 0.35µm digital CMOS. Both PR4 and EPR4 detectors
are supported. Digital servo emulates traditional analog servo detection and
supports matched filter and DI-bit Gray code detection for 3dB SNR improvement.
The read channel dissipates 1.1W at 360Mb/s.
| 2.5 | 260Mb/s Mixed-Signal Single-Chip Integrated System Electronics for Magnetic Hard Disk Drives | 3:45 PM |
S. Nemazie, A. Khan, K. Popat, D.-N. Le, S. Chang, W. Foland1,
K. Kwan, J. Yu, S. Yang, R. McPherson1, V. Dujari, H.
Futakami1,
D. Bonomi2, M. Wei1, B. Scott2
Cirrus Logic, Inc., Fremont, CA / 1Austin, TX /
2Broomfield, CO
This mixed-signal IC integrates four of the major VLSI functions in magnetic
HDD systems including: a read channel, an ATA hard disk controller, a
micro-controller (with an ARM7TDMI RISC uP, ROM, RAM) and a motion-control
servo block.
| 2.6 | A 3V 10-100MHz Continuous-Time Seventh-Order 0.05 o Equiripple Linear-Phase Filter | 4:15 PM |
N. Rao, V. Balan, R. Contreras
DataPath Systems, Inc., Los Gatos, CA
A 3V continuous-time read channel filter has a 10-100 MHz programmable lowpass
corner, provides up to 13dB magnitude boost, and up to ±30% group delay
asymmetry. The filter in 0.29µm BiCMOS occupies 0.5mm2 and
dissipates 120mW at 100MHz.
| 2.7 | A 300Mb/s BiCMOS Disk-Drive Channel with AdaptiveAnalog Equalizer | 4:30 PM |
A. Bishop, I. Chan1, S. Aronson2, P. Moran, K.
Han2, R. Cheng2,
K. Fitzpatrick2, J. Stander, R. Chik1, K. Kshonze, M.
Aliahmad1,
J. Ngai, H. He, E. daVeiga2, P. Bolte2, C.
Krasuk2, B. Cerqua,
R. Brown1, P. Ziperovich2, K.
Fisher2
Quantum Corp., Shrewsbury, MA / 1 Kanata, Canada /
2Milpitas, CA
A complete disk-drive read/write channel incorporates a continuous-time analog
equalizer, combining the equalizer with the Nyquist filter. This mixed-signal
BiCMOS chip operates on data rates up to 300Mb/s, and is optimized for data
densities from 1.8 to 3.0 bits.
| CONCLUSION | 4:45 PM |
Chair: J. Fattaruso, Texas Instruments, Dallas, TX
Associate Chair: K. Martin, Univ. of Toronto, Toronto, Canada
| 3.1 | A 1.5V 1.0mW Audio [Sigma][Delta] Modulator with 98dB Dynamic Range | 1:30 PM |
A. Coban1, 2, P. Allen1
1Georgia Institute of Technology, Atlanta,
GA
2Rockwell Semiconductor Systems, Newport Beach, CA
An audio-quality fourth-order SC [Sigma][Delta] modulator dissipates 1.0mW with
a 1.5V supply. Clocked at 2.82MHz, it achieves 98.2dB dynamic range in a 20kHz
bandwidth. Peak SNR and SNDR are 90 and 88dB, respectively. A fully
differential circuit uses standard 0.5µm 3-metal 1-poly n-well CMOS with
metal-poly capacitors.
| 3.2 | A 1.8mW CMOS [Sigma][Delta] Modulator with Integrated Mixer for A/D Conversion of IF Signals | 2:00 PM |
L. Breems, E. van der Zwan1, E. C. Dijkmans1, J.
Huijsing
Delft University of Technology, Delft, The Netherlands
1Philips
Research Lab., Eindhoven, The Netherlands
An IF [Sigma][Delta] modulator for radio receivers in 0.35µm CMOS combines
an IF mixer and an anti-aliasing filter with a continuous-time baseband
[Sigma][Delta] modulator. The dynamic range is 82dB in a 100kHz bandwidth and
the IP3 is +36dBV. Power consumption is 1.8mW from a 2.5V supply.
| 3.3 | A Nyquist-Rate Pipelined Oversampling A/D Converter | 2:30 PM |
S. Paul1, 2, H.-S. Lee2, J. Goodrich2, T.
Alailima1, D. Santiago1
1MIT Lincoln Lab., Lexington, MA
2Massachusetts Institute of Technology, Cambridge, MA
An ADC architecture samples with a pipelined structure at Nyquist rate but
implements a spatial oversampling algorithm. A prototype chip using CCD
elements in standard 1.2µm CMOS achieves 74dB SNR sampling an 8MHz signal
at an 18MHz data rate. DNL is <±0.15LSB at 13b.
| BREAK | 3:00 PM |
| 3.4 | A Sixth-Order Continuous-Time Bandpass [Sigma][Delta] Modulator for Digital Radio IF | 3:15 PM |
J. van Engelen, R. van de Plassche, E. Stikvoort1, A.
Venes1
Eindhoven Univ. of Technology, Eindhoven, The
Netherlands
1Philips Research Labs., Eindhoven, the
Netherlands
A sixth-order continuous-time bandpass [Sigma][Delta] ADC tuned at 10.7MHz and
sampled at 40MHz achieves 67dB SNDR at 200kHz and 80dB in 9kHz. The IM3 is 82dB
below carrier level. The 0.5µm CMOS chip occupies 0.9x0.4mm2
and consumes 60mW at 3.3V (digital) and 5V (analog). The sample frequency range
is 40-80MHz.
| 3.5 | A Bandpass Mismatch-Shaped Multibit [Sigma][Delta] Switched- Capacitor DAC Using Butterfly Shuffler | 3:45 PM |
H. Lin, R. Schreier
Oregon State University, Corvallis, OR
An analytical model of a butterfly shuffler is the basis for a general
mismatched-shaping shuffler scheme. A bandpass multi-bit [Sigma][Delta] SC DAC
with 90dB dynamic range at 125kHz center frequency using the shuffler has
harmonic distortion reduced by up to 2dB. The distortion of a bandpass multibit
[Sigma][Delta] DAC is reduced by 27dB with a second-order bandpass
mismatch-shaping shuffler. The prototype achieves a 90dB dynamic range and a
125kHz center frequency.
| 3.6 | A 100MHz IF, 400MSample/s CMOS Direct-Conversion Bandpass [Sigma][Delta] Modulator | 4:15 PM |
H. Tao, J. Khoury
Columbia University, New York, NY
A CMOS [Sigma][Delta] modulator using an embedded direct-conversion
architecture digitizes a 200kHz passband centered at 100MHz, and produces
baseband I/Q outputs with 54dB peak SNR. Images due to I/Q mismatches are
suppressed by 50dB. The 0.35µm digital CMOS chip operates from a
2.7/3.3V supply, dissipates 330mW and occupies 3.2mm2.
| 3.7 | A 400MHz 12b 18mW IF Digitizer with Mixer Inside a [Sigma][Delta] Modulator Loop | 4:45 PM |
A Namdar, B. Leung
University of Waterloo, Ontario, Canada
A 0.8µm BiCMOS 400MHz IF digitizer based on embedding a down- conversion
mixer in a [Sigma][Delta] modulator achieves 12b resolution for 40kHz bandwidth
and dissipates 18mW. The modulator has HD3 <-90dB (-4dB input)
and IM3 <-70dB for a -8 dB input.
| CONCLUSION | 5:15 PM |
Chair: J. Sevenhans, Alcatel, Antwerpen, Belgium
Associate Chair: K. Najafi, Univ. of Michigan, Ann Arbor, MI
| 4.1 | How SiGe Evolved Into a Manufacturable Semiconductor Production Process | 1:30 PM |
S. Subbanna, D. Ahlgren, D. Harame1, B.
Meyerson2
IBM Microelectronics, Hopewell Jct., NY / 1Burlington,
VT
2IBM Research, Yorktown Heights, NY
SiGe HBT Technology, a 50GHz silicon-based 0.5µm BiCMOS production
technology, extends the wired and wireless network application space of
silicon-based technology. Fifteen years of research and development makes this
possible. Tradeoffs make the technology robust and mainstream-CMOS compatible.
| 4.2 | A DECT Transceiver Chip Set Using SiGe Technology | 2:00 PM |
M. Bopp
TEMIC Semiconductor GmbH, Heilbronn, Germany
A two-chip bipolar RF transceiver for DECT includes power amplifier, low-noise
amplifier, and fully integrated VCO. Non-blind-slot and multislot capability is
obtained by closed-loop modulation. Supply range is from 2.7 to 5V without
mechanical tuning. Fewer than 50 peripheral passive components are used.
| 4.3 | Monolithic CMOS Distributed Amplifier and Oscillator | 2:30 PM |
B. Klevaland, C. Diaz1, D. Vook2, L.
Madden3, T. Lee, S. Wong
Center for Integrated Systems, Stanford University, Stanford,
CA
1Taiwan Seimconductor Manufacturing Co.,
Taiwan
2 Hewlett-Packard Labs., Palo Alto, CA
3MIPS
Technologies, Inc., Mountain View, CA
A 90mW CMOS distributed amplifier with 5dB gain has 13GHz unity-gain cutoff
frequency. A 52mW 17GHz CMOS distributed oscillator with -2.5dBm output power
has -118dBc/Hz phase noise at 1MHz offset. The circuits in 0.18µm CMOS
with four Al-Cu metal layers occupy 0.2x3.3mm2 and
0.3x1.5mm2, respectively. On-chip coplanar stripline inductors
permit low-loss signal propagation over a low-resistivity silicon
epi-substrate.
| 4.4 | Fully-Integrated CMOS RF Amplifiers | 2:45 PM |
B. Ballwebber, R. Gupta1, D. Allstot2
Oregon State University, Corvallis, OR
1 Maxim Integrated
Products, Sunnyvale, CA
2Arizona State University, Tempe, AZ
A fully-integrated four-stage distributed amplifier with 6.5dB gain and 5.5GHz
bandwidth, and a balanced power amplifier delivers 85mW at 900MHz with 55%
drain efficiency in 0.6µm digital CMOS operating from a single 3V supply.
Custom CAD optimizes design, including active and passive device and package
parasitics.
| BREAK | 3:00 PM |
| 4.5 | High-Frequency Analog Filters in Deep-Submicron CMOS Technology | 3:15 PM |
R. Castello, I. Bietti1, F. Svelto2
Universita' di Pavia, Pavia, Italy
1STMicroelectronics, Milan,
Italy
2Universita' di Bergamo, Dalmine, Italy
A 7th-order programmable gm-C filter uses 0.35µm CMOS with
160MHz maximum pole frequency. Techniques used increase the bandwidth of
gm-C filters in scaled technologies, while preserving dynamic range
and accuracy. GHz passive filters are based on master-slave tuning.
| 4.6 | Analog Broadband Communication Circuits in Pure Digital Deep-Sub-Micron CMOS | 3:45 PM |
K. Bult
Broadcom Corp., Irvine, CA
Voltage scaling is a problem for A/D and D/A converters integrated with digital
circuits in 0.5µm CMOS. Techniques permit 10b 100MSample/s ADC designs
operating from 2.5V supply. With thick oxide and zero VT, these
designs may be practical for 5 years to overcome voltage scaling problems in
A/D and D/A converters integrated with digital circuits in 0.5µm CMOS.
| 4.7 | Tunable, Switchable, High-Q VHF Microelectromechanical Bandpass Filters | 4:15 PM |
T. C. Nguyen, A.-C. Wong, H. Ding
University of Michigan, Ann Arbor, MI
High-Q VHF micromechanical filters, each comprised of a network of tens of
µm vibrating mechanical beams, are demonstrated in an IC-compatible
surface-micromachining technology with sufficient tunablity and on-off
switchability for use in an RF preselect transceiver architecture for Legacy
radio applications.
| 4.8 | A 1.9GHz Micromachined-Based 126dBc/Hz CMOS VCO | 4:45 PM |
A. Dec, K. Suyama, Epoch Technologies, L.L.C., White Plains, NY
A 1.9GHz CMOS VCO is based on micromachined electro-mechanically tunable
capacitors and bond-wire inductors. The VCO has 9% tuning range and -126dBc/Hz
phase noise at a 600kHz offset from the carrier. Operating from a 2.7V power
supply, VCO and output buffers consume 15mW and 30mW, respectively.
| 4.9 | An Analog CMOS IC for Template Matching | 5:00 PM |
A. Biyabani, R. Carley, T. Kanade
Carnegie Mellon University, Pittsburgh, PA
A 3V 0.5µm CMOS analog IC corelates each 9x9 pixel window in an input
image with 8 templates at rates up to 5MHz for the best match. The total signal
processor consumes 420mW.
| CONCLUSION | 5:15 PM |
Chair: W. Bowhill, Compaq Computer Corp., Shrewsbury, MA
Associate Chair: K. Bernstein, IBM Microelectronics,
Essex Junction, VT
| 5.1 | A 500MHz 64b RISC CPU with 1.5MB On-Chip Cache | 1:30 PM |
P. Barnes
Hewlett-Packard Co., Fort Collins, CO
A 64b PA-RISC microprocessor is migrated to 0.25µm CMOS and integrated
with on-chip 1.0MB L1 data and 0.5MB L1 instruction caches. The 500MHz
processor incorporates 140M FETs on a 21.3x22mm2 die and delivers
>25 SPECint95 and >40 SPECfp95 at 360MHz.
| 5.2 | 600MHz G5 S/390 Microprocessor | 2:00 PM |
G. Northrup, R. Averill, K. Barkley, S. Carey, Y. Chan, Y. H. Chan,
M. Check, D. Hoffman, W. Huott, B. Krumm, K. Krygowski,
J. Liptay, M. Mayo, T. McNamara, T. McPherson, E. Schwarz,
L. Sigal1, T. Slegel, C. Webb, D. Webber, P. Williams
IBM Systems 390 Div., Poughkeepsie, NY
1IBM Research Div.,
Yorktown Heights, NY
A microprocessor in 0.15µm Ieff process technology operating up
to 600MHz for an IBM S/390 G5 Enterprise server and at 500MHz in a 10+2 shared
microprocessor environment consists of two instruction units with a branch
target buffer, two execution units including a floating-point unit supporting
both hex and binary operations, a buffer control containing L1 cache and
register checkpoint. Full custom and semicustom design are exploited.
| 5.3 | Storage Hierarchy to Support a 600MHz G5 S/390 Microprocessor | 2:30 PM |
P. Turgeon
IBM Corp, Poughkeepsie, NY
The IBM S/390 G5 server features a microprocessor operating to 600MHz. An SMP
system comprised of up to 12 microprocessors has significant cache and memory
bandwidth requirements. Bi-nodal cache hierarchy features fast-access L1 and L2
caches, shared caching at L2 level, and switch-based interconnection
network.
| BREAK | 3:00 PM |
| 5.4 | A 7th-Generation x86 Microprocessor | 3:15 PM |
V. Andrade, R. Burd, G. Constant, J. Correll, M. Crowley, M. Golden, S.
Hesley, N. Hopkins, S. Johnson, R. Khondker, D. Meyer,
J. Moench, H. Partovi, R. Posey, F. Weber, J. Yong
Advanced Micro Devices, Austin, TX
A 7th generation x86 microprocessor fetches,decodes, and retires three x86
instructions per cycle in a 15-stage pipeline. The chip uses 0.25µm
six-layer metal CMOS plus tungsten local interconnect.
| 5.5 | An Out-of-Order Three-Way Superscalar Multimedia h5 Floating-Point Unit | 3:45 PM |
M.
Golden, N. Juffa, S. Meier, S. Oberman, H. Partovi, A. Scherer,
F. Weber
Advanced Micro Devices, Sunnyvale, CA
An x87-compatible out-of-order superscalar floating-point unit in 0.25µm
six-layer-metal CMOS executes traditional floating-point instructions at two
FLOPS per cycle peak rate, 3DNow! SIMD instructions at four FLOPS per cycle
peak rate, and up to three MMX SIMD instructions per cycle.
| 5.6 | A 450MHz PowerPC TM Microprocessor with Enhanced Instruction Set and Copper Interconnect | 4:15 PM |
J. Alvarez, E. Barkin, C.-C. Chao, B. Johnson, M. D'Addeo,
F. Lassandro, C. Nicoletta, P. Patel, P. Reed, D. Reid, H. Sanchez,
J. Siegel, M. Snyder, S. Sullivan, S. Taylor, M. Vo
Motorola Somerset Design Center, Austin, TX
A 450MHz 7W microprocessor with an AltiVecTM instruction set
implementation and high memory bandwidth is fabricated in 1.8V CMOS with copper
interconnect. A crossbar circuit that implements the permute instruction and a
programmable 3.3/2.5/1.8V I/O buffer are used. The 10.5M-transistor chip on a
83µm2 die has estimated SPECint95 and SPECfp95 performance of
20.
| 5.7 | A 600MHz IA-32 Microprocessor with Enhanced Data Streaming for Graphics and Video | 4:45 PM |
R. Senthinathan, S. Fischer, H. Rangchi, H. Yazdanmehr
Intel Corp., Folsom, CA
A next-generation P6 microprocessor adds 67 instructions for data streaming.
Circuit enhancements include multi-grid C4 power distribution, decoupling
techniques, improvements in dynamic circuits, and process voltage and
temperature-compensated I/O buffer designs. The processor in 0.25µm
5-layer-metal CMOS achieves 600MHz.
| CONCLUSION | 5:15 PM |
| 6.1 | A Sub-40ns Random-Access Chain-FRAM Architecture with 7ns Cell-Plate-Line Drive | 1:30 PM |
D. Takashima, S. Shuto1, I. Kunishima1, H.
Takenaka2, Y. Oowaki,
S. Tanaka1
Toshiba Corp., Yokohama / 1Kawasaki
2Toshiba
Microelectronics Corp., Yokohama, Japan
A prototype 16kb nonvolatile chain FRAM uses 0.5µm 2-metal CMOS
technology. At 3.3V, read/write cycle and random-access times are 80 and 37ns,
respectively. Using a folded cell plate line drive technique, plate line drive
is 7ns.
| 6.2 | A 0.5µm 3V 1T1C 1Mb FRAM with a Variable Reference Bitline Voltage Scheme Using a Fatigue-Free Reference Capacitor | 2:00 PM |
T. Miyakawa, S. Tanaka, Y. Itoh, Y. Takeuchi, R. Ogiwara,
S. Doumae, H. Takenaka1, I. Kunishima, S. Shuto, O. Hidaka,
S. Ohtsuki1, S-i. Tanaka
Toshiba Corp., Yokohama, Japan
1Toshiba Microelectronics Corp.,
Yokohama, Japan
A 3V 1T1C 1Mb FRAM achieves 160ns read-access time. A
variable-reference bitline voltage tracks the polarization distribution of cell
capacitors via a fatigue-free reference capacitor. A double wordline pulse
sensing is used for imprint immunity.
| 6.3 | Multi-Level Technologies for FRAM Embedded Reconfigurable Hardware | 2:30 PM |
K. Asari1,2,4, Y. Mitsuyama2, T.
Onoye2, I. Shirakawa2, H. Hirano1,
T. Honda1, T. Otsuki1, T. Baba3, T.
Meng4
1Matsushita Electronics Corp., Osaka, Japan
2Osaka University, Osaka, Japan
3Panasonic
Technologies Inc., Cupertino, CA
4Stanford Univ., Stanford, CA
Non-volatile FRAM is used as the building block for reconfigurable
architectures. Overall power is reduced 30% and area is saved using low voltage
to store and access RAM data superimposed on less-frequently accessed ROM data
in the same cell.
| 6.4 | Multi-Phase Driven Split Word-Line-Ferroelectric Memory Without Plate Line | 2:45 PM |
H. Kang, D. Kim1, K. Oh, J. Roh, J. Kim, J. Ahn, H. Lee, D.C.
Kim2,
W. Jo2, H.M. Lee2, S.M. Cho2, H.J.
Nam2, J.-W. Lee2, C.-S. Kim2
LG Semiconductor, Ltd., Gheongju-si, Korea
1Pohang University
Sci. and Tech., Pohang, Korea
2LG Corp. Institute of Technology,
Seoul, Korea
Conventional cell plate lines are eliminated in a cell accessed via
multi-phase voltage-driven split word lines, resulting in an area reduction
compared to divided plate cell lines. Cell access time is determined by
<10ns split word line rise time.
| BREAK | 3:00 PM |
| 6.5 | A 256Mb Multilevel Flash Memory with 2MB/s Program Rate for Mass Storage Application | 3:15 PM |
A. Nozoe, H. Kotani, T. Tsujikawa, K. Yoshida, K. Furusawa, M. Kato, T.
Nishimoto, H. Kume, H. Kurata, N. Miyamoto1, S. Kubono2
M. Kanamitsu2, K. Koda3, T. Nakayama3, Y.
Kouro3, A. Hosogane3,
N. Ajika3, K. Kobayashi3
Hitachi, Ltd., Tokyo, Japan/ 1Hitachi Device Eng. Co., Ltd., Tokyo,
Japan
2Hitachi ULSI Engineering Corp., Tokyo,
Japan
3Mitsubishi Electric Corp., Hyogo, Japan
A 256Mb flash memory using 0.25µm-poly, 3-metal technology and
multilevel cell (2b/cell) and architecture gives 138.6mm2 die. The
read access time is 50µs in data transfer and 50ns in serial cycle. The
program/erase time is 1ms/sector.
| 6.6 | A 130mm 2 256Mb NAND Flash with Shallow Trench Isolation Technology | 3:45 PM |
K. Imamiya, Y. Sugiura, H. Nakamura, T. Himenio, K. Takeuchi,
T. Ikehashi, K. Kanda, K. Hosono, R. Shirota, S. Aritome, K. Shimizu, K.
Hatakeyama, K. Sakui Toshiba Corp., Yokohama, Japan
A 130mm2 256Mb flash memory uses 0.25µ m triple-well
technology. NAND cell architecture gives a 0.29µm2 cell. A
shielded bit line scheme and a reduced bit line swing gives 3.8µs read
first access time and 35ns cycle time. The program time is 200µs/page.
| 6.7 | A 29mm 2 1.8V-Only 16Mb DINOR Flash Memory with Gate-Protected Poly-Diode Charge Pump | 4:15 PM |
M. Mihara, Y. Miyawaki, O. Ishizaki, T. Hayasaka, K. Kobayashi,
T. Omae, H. Onoda, H. Kimura, Y. Kawajiri1, M. Wada1,
H. Sonoyama1, J. Etoh2
Mitsubishi Electric Corp., Itami Hyogo, Japan
1Hitachi ULSI
Systems Co., Ltd. / 2Hitachi, Ltd., Tokyo, Japan
A 29mm2 16Mb divided bit line NOR (DINOR) is fabricated
using 0.25µ m triple well 3-layer metal technology. Read access time is
82ns at 1.8V. A poly diode charge pump technique improves pump efficiency and
eliminates the body effect problem.
| 6.8 | A 3.3V 90MHz Flash Memory Module Embedded in a 32b RISC Microcontroller | 4:45 PM |
M. Hiraki, T. Tanaka, Y. Shinagawa1, K. Suzukawa1, M.
Fujito1,
Y. Kawai1, D. Mishina1, T. Ohshima, S.
Abe2, H. Kubota2, T Yamaki,
S. Takuma, K. Shiba, K. Kuroda, H. Ohsuga2, K.
Masujima2,
K. Matsubara2
Semicon. Tech. Devel. Div., Hitachi, Ltd., Tokyo, Japan
1Hitachi
ULSI Systems Co., Ltd., Tokyo, Japan
2System LSI Business Div.,
Hitachi, Ltd., Tokyo, Japan
A 32kB embedded flash memory module uses 0.35µm technology for 32b
RISC microcontroller. This module operates at 90MHz with 3.3V supply, using
shielded bit line and symmetrical bit line architecture with a differential
sense amplifier.
| CONCLUSION | 5:15 PM |
| ME1 | "They Don't Make Engineers Like They Used To. ...?" |
| (Salon 10 - 15) |
Moderator/Organizer: Thomas Lee, Stanford Univ., Stanford, CA
Co-organizer: Mary Jo Nettles, AMCC, San Diego, CA
Education of most engineers used to involve a strong hardware component. Slide
rules reinforced a connection to physical reality by gently refusing to provide
orders of magnitude. However, with the complexity of modern circuits, have
come similarly complex simulation tools. Are today's engineers getting the
education they need to do the job right? Has SPICE really caused mindless
simulation to displace creative thought? Or have such tools made engineers more
productive? Or both? And if we were to educate engineers "better," would they
be any more employable?
Panelists
Hugo De Man, Katholieke Universiteit, Leuven, Belgium
Nicky Lu, ETRON Technology, Hsinchu, Taiwan, R.O.C.
Bob Pease, National Semiconductor, Santa Clara, CA
Behzad Razavi, UCLA, Los Angeles, CA
Charles Sodini, MIT, Cambridge, MA
Eric Swanson, Crystal Semiconductor, Austin, TX
| ME2 | The Single-Chip Digital Mobile Radio: Does it Really Make Sense? |
| (Salon 9) |
Organizer/Moderator: Ernesto Perea, STMicroelectronics, Croilles,
France
Co-Organizer: Rudy Van de Plassche, Eindhoven Univ. of
Technology, Eindhoven, The Netherlands
Is a single-chip digital mobile radio impossible, or a difficult problem? Does
"single-chip radio" mean RF front-end integration, signal converters and even
the DSP? Does it mean integration of receiver and transmitter? What
frequency-band, modulation, channel bandwidth and specific requirements are
implied? Tradeoffs of hardware/software, GaAs/Bi/CMOS/BiCMOS,
single-chip/single-package, on-chip/off-chip passives (no passives?) impact
cost. What is expected from coupling reduction and passive component quality,
advanced materials, semiconductor, processing, packaging or MEMs? What about
external constraints, such as battery life, weight and volume, and EMC
considerations?
Panel:
Joseph Fenk, Siemens Semiconductor Group, Munich, Germany
Sven Mattison, Ericsson Mobile Communications, Lund, Sweden
Jan Sevenhans, Alcatel, Antwerpen, Belgium.
Michiel Steyaert, Katholieke Universiteit, Leuven, Belgium
Ton Wagemans, Philips Res. Labs, Eindhoven,The Netherlands
Werner Gruber, Nokia, Tew Technology Sourcing, Salo, Finland
Ken Hanson, Motorola, Austin, TX
| ME3 | SRAMs in the Early 21st Century |
| (Salon 8 ) |
Moderator: Don Draper, Advanced Micro Devices, Sunnyvale, CA
Organizer: Ban-Pak Wong, Sun Microsystems, Palo Alto, CA
The panel debates how the SRAM stream will change as it meanders its way
towards the 21st century. What is the future for standalone SRAMs? Are there
incentives to market standalone SRAMs? Are they approaching technology scaling
limits? Is it purely economics or the lagging in technology, that has caused
SRAMs to fall off Moore's curve? There also are issues of embedded SRAMs
versus standalone SRAMs to satisfy the appetite for a low-latency L2 cache for
high-performance processors. Does this ever-increasing need for embedded SRAMs
leave standalone SRAMs behind like oxbow lakes?
Panel:
Tony Alvares, Cypress Semiconductor, San Jose, CA
Geordie Braceras, IBM, Essex Junction, VT
J. Thomas Pawlowski, Micron, Boise, ID
David Chapman, Motorola, Austin, TX
Hyun-Geun Byun, Samsung, Yongin City, Kyungki, Korea
Steven Eliscu, IDT, Santa Clara, CA
| ME4 | The Best and Worst in the Evolution of Digital IC Design |
| (Salon 7 ) |
Moderator/Organizer: John Maneatis, JGM Enterprises, Redwood City, CA
Co-organizer: Kevin Donnelly, Rambus, Mountain View, CA
This panel addresses the best and worst innovations of digital IC design,
focusing on what is sometimes a fine line between the good, the bad, and the
absurd. While short-term necessity drives most innovations, many have had
significant long-term impact on the industry. Therefore, rather than just dry
recitation of historical facts, the panel maintains a forward-looking
perspective on applicability of the innovations to future design challenges,
and includes views expressed by the audience.
Panel:
Bill Bidermann, Chromatic, Sunnyvale, CA
Mark Horowitz, Stanford Univ., Stanford, CA
Mark Johnson, Rhombus, Menlo Park, CA
Toshiaki Masuhara, Hitachi, Tokyo, Japan
Peter Stoll, Intel, Albuquerque, NM
Christer Svensson, Linköping Univ, Linköping, Sweden