This Short Course is intended to jumpstart engineers in the design and development of Gigabit local area networks (LAN) over four pairs of Category-5 unshielded twisted pair (UTP) cables. Course completion provides an overall perspective of system architectures and specifications and a detailed description of possible circuit and system designs of 1000BASE-T transceivers. Topics covered include frequency response and noise characteristics of the four-pair CAT-5 UTP transmission medium, cross-talk and echo-cancellation methods, multi-level data detection and error-correction schemes, multi-level clock recovery and phase-locking techniques, and analog interface issues. Emphasis is on CMOS circuit and system implementation.
For Registration, please use the ISSCC99 Registration Form on the Advance Program Centerfold. Sign-in is at San Francisco Marriott Hotel, Level B-2, beginning at 8:00 AM.
The Short Course will be offered three times on Thursday, February
18.
The challenges inherent in implementing Gigabit Ethernet over four pairs of CAT-5 unshielded twisted pair cabling are presented. The noise environment on CAT-5 UTP cabling are described and system design approaches for achieving reliable gigabit transmission in such environments are provided. Particular emphasis is given to the technical foundations of the 1000BASE-T standard for Gigabit transmission over CAT-5 cabling.
Instructor: Sailesh Rao, Level One Communications, Inc., Morganville, NJ, received B. Tech. from IIT Madras, India (1981), MSEE from SUNY Stony Brook (1982), and PhD from Stanford (1985). He was with AT&T Bell Labs (1985-1991) and Silicon Design Experts (1991-1996). Since 1996, he has been with Level One Comm. developing architectures/devices for LAN/WAN. He contributed to the ATM-155, 100BASE-T2, and 1000BASE-T standards.
1000 Mb/s full-duplex data transfer over four unshielded twisted pairs is presented. A key component of Gigabit Ethernet is the parallel encoding and detection of data symbols on the four twisted pairs. The signal processing and hardware implications of this signaling scheme on the near-end cross talk canceller, echo canceller, decision feedback equalizer and Viterbi detector will be discussed.
Instructor: Jack Kenney, Analog Devices, Inc., Somerset, NJ, received BS degrees from Providence College and Columbia in 1984. He was with Codex Corp. (1984-86), and Carnegie Mellon U. (1986-91) conducting MS and PhD research on decision feedback equalization for hard disk drives and high-order multi-bit [Sigma][Delta] converters. He was an Assoc. Prof. of ECE at Oregon State U. from 1992-97. Currently, he designs analog front ends for xDSL modems.
Clock recovery techniques for multi-level baseband signals in the presence of severe inter-symbol-interference are presented. Several different clock recovery implementations with analog, digital or mixed-mode PLL are compared. Fast locking algorithms and loop filter optimization for the PLL are introduced. Finally, circuit designs for the critical VCO and phase/frequency detector PLL components are discussed.
Instructor: Beomsup Kim received BSEE (1983) and MSEE (1985) from Seoul National U. and PhD from UC Berkeley (1990). He was with Chips and Technologies, Inc. from 1990-91 and with Philips Research Labs from 1991-93. Since 1994, he has been Assoc. Prof. with Korea Advanced Institute of Science and Technology. His interests include mixed-mode signal processing for telecom, disk drive, and LAN. He was co-recipient of the 1991 IEEE JSSC Best Paper Award.
Design issues relating to analog interfaces in Gigabit Ethernet twisted-pair and fiber-optic transceivers. Emphasis is on CMOS implementations of echo cancellation, equalization, and A/D conversion in the context of twisted-pair transceivers. Optical receiver design focuses on transimpedance amplifiers and clock recovery circuits. Design examples reveal trade-offs at both architecture and circuit levels.
Instructor: Behzad Razavi received PhD EE from Stanford in 1992 and worked at AT&T Bell Labs and HP Labs before joining UCLA as an Assoc. Prof. in 1996. He has received awards at ISSCC and ESSCIRC and published three books in the area of analog and RF design. His current research includes high-speed data communication interfaces, RF transceivers and synthesizers, and data converters.