TECHNOLOGY DIRECTIONS
1998 ISSCC - TECHNOLOGY DIRECTIONS
Subcommittee Chair:
Timothy Tredwell, Kodak, Rochester, NY.
HIGHLIGHTS
- Processor architectures, deep-submicron circuits, and optical interconnects for future generations of computers [TP6]
- High-speed, low-power sub-0.5V digital circuits, and sub-1.0V analog circuits [FP12]
- Advanced RF circuits [FP16]
- Integrated passive components and low-loss substrates improve GHz RF circuits [16.1]
- Deep-submicron RF CMOS circuits [16.5]
MOST-SIGNIFICANT RESULTS
- Advanced processor architectures and deep-submicron digital circuits [TP6]
- 0.08-micron gate-length CMOS test chip utilizing substrate over-biasing to achieve 40ps gate delay at 0.5V [6.2]
- Low power/low voltage circuits [FP12]
- Sub-1V Op Amp [12.1]
- 0.5V 320MHz 8b Gate-Array MUX/DEMUX [12.2]
- Advanced RF circuits [FP16]
- High-Q (~ 40) on-chip inductors [16.1, 16.2, 16.3]
- 10-GHz RF circuits in 0.08-micron CMOS [16.5]
APPLICATIONS
- PCs, workstations and embedded processors with continued performance growth [TP6]
- Low-power portable equipment [FP12]
- Wireless LAN and GSM transceivers, K-band microwave MMICs [FP16]
ECONOMIC AND SOCIAL IMPACT
- Mobile communications and computing
- Ubiquitous high-bandwidth wireless communication
- Computing systems with continued growth in performance
Session:
TP6 Subcommittee: Technology Directions
Technology Directions: Deep Sub-micron and Digital Directions
Chair: D. Draper, Advanced Micro Devices, Sunnyvale, CA.
Associate Chair: T. Baba, Matsushita Semiconductor of America, Palo Alto, CA.
DRIVERS
- The future of digital computing will require architectural innovation, deep-sub micron circuits and advanced interconnect strategies to continue the present rate of performance improvement
- Innovations required in microprocessor architecture to drive performance improvements beyond superscalar RISC
- Deep-submicron circuits required for next generation of processors and memories, but pose substantial circuit-design and simulation challenges
- Optical chip-to-chip interconnect for high bandwidth
- Revolutionary technologies required to achieve massively-parallel computing systems with acceptable power dissipation
- Neural processors
- Quantum computing
HIGHLIGHTS
- Architectures beyond superscalar RISC [6.1]
- Advanced compilers to extract program parallelism
- Dynamic learning in hardware and software
- Deeper pipelines and many levels of on-chip cache
- Multi-threading of two or more instruction streams
- A sub-0.1micron circuit design with substrate over-biasing [6.2]
- Test chip with 0.08-micron gate length fabricated with X-ray lithography
- Threshold voltage roll-off with gate length reduced to less than half that achieved without substrate over-biasing
- Gate delay of 40ps achieved at 0.5 volts
- Statistical circuit characterization for deep-sub micron circuits [6.3]
- Separates stochastic from systematic sources of variation
- Multi-chip module with optical interconnection for parallel-processor system [6.4]
- Parallel-processor system developed for Monte-Carlo simulation includes:
- Parallel software and compiler for Monte Carlo simulation
- Processor chip utilizing VLIW and ring-bus interface
- Optical waveguide interconnect on MCM with bump-micro-mirrors to couple signals into processors
- A 1-Million-Synapse Self-Learning Digital Neural-Network Chip [6.5]
- Uses Sparse-Memory-Access architecture to reduce unnecessary operations
- A 0.25micron chip with 64 processing units and 1 Mword x 16b memory achieves 10 gigaconnections per second
- Bulk-Spin Quantum Computation: Towards Large-Scale Quantum Computation [6.6]
- Demonstrated simple quantum circuits using nuclear magnetic resonance
- Combined with micro-machined magnets and coils on-chip may deliver future quantum computers
Session:
FP12 Subcommittee: Technology Directions
LOW-VOLTAGE AND MULTI-LEVEL TECHNIQUES
Chair:
Bang-Sup Song, University of Illinois, Urbana, IL.
Associate Chair:
Jan van der Spiegel, University of Pennsylvania, Philadelphia, PA.
DRIVERS
- Low-power portable devices
- High-speed image processing
- High-speed high-density memory/logic interface
HIGHLIGHTS
- Sub-1V CMOS op amp [12.1]
- 0.5V, 320MHz gate array [12.2]
- 0.5V low-leakage CMOS circuits [12.3, 12.4]
- Small-area 4-valued logic in memory [12.5]
- Large-kernel high-throughput image filtering at 1.5 Tera- computations per second [12.6]
Session:
FP16 Subcommittee: Technology Directions
Advanced Radio-Frequency Circuits
Chair:
Ernesto Perea, SGS-THOMSON Microelectronics, Crolles, France
Associate Chair:
Glenn Gulak, University of Toronto, Ontario, Canada
DRIVERS
- Higher Q-factor inductors for improved selectivity and noise performance at lower power consumption
- Low-loss substrates for improved passive device performance and multi-GHz applications
- Novel integrated strip-lines on Si for K-band operation
HIGHLIGHTS
- Q=40, 0.5nH to100nH inductors on Si [16.1, 16.2]
- -142dBc/Hz NF at 10MHz offset, 1GHz VCO [16.2]
- 2.5GHz zero-IF WLAN SOA receiver [16.3]
- 3D Masterslice k-band Si MMIC [16.4]
- Sub-0.1um CMOS for multi-GHz applications [16.5]
- Fractal capacitors for 3x increase of capacitance/unit area [16.6]
- 10GHz RTD-based ADC [16.7]
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Last modified : Tuesday February 17, 1998 at 8:12am EST