SIGNAL PROCESSING
- Daytime Paper Sessions
- Evening Panel Discussion
- Tutorial
- Trend Chart
1998 ISSCC - SIGNAL PROCESSING
Subcommittee Chair:
Rajeev Jain, UCLA, Los Angeles, CA.
HIGHLIGHTS
- Video and multimedia processors [TP2]
- Low-power signal processing [FA7]
- Disk-drive signal processing [SP24]
MOST- SIGNIFICANT RESULTS
- 0.95W MPEG2 encoder breaks the one-watt barrier [2.1]
- 150uW encryption processor [7.2]
- 21mW, 360Mb/s disk drive detector [24.3]
APPLICATIONS
- Low-power video compression enables digital camcorders
- Ultra-low-power processor enables portable encryption
- Portable computers getting desktop-like storage capacities
ECONOMIC AND SOCIAL IMPACT
- Digital camcorders greatly simplify PC-based home-video editing
- Secure communication available to mobile users
- Bring all your desktop data on the road
PANEL
- How Will Media Signal Processors Dominate the Next Decade? [FE6]
TUTORIAL
- FIR-1001: Filter Architectures and Applications, [T4]
Session:
TP 2 Subcommittee: Signal Processing
Video and Multimedia Signal Processing
Chair: Kumar Ganapathy, Rockwell Semiconductor Systems, Newport Beach, CA.
Associate Chair:
Yasushi Ooi, NEC Corporation, Kanagawa, Japan
DRIVERS
- Low-cost consumer applications
- Higher levels of integration
- Low-power, low-voltage designs for portable video communications
- Higher-resolution low-cost solutions for digital TV applications
- High-quality digital-audio and video broadcasting
HIGHLIGHTS
- Single-chip implementation of MPEG2 (MP@ML) video encoding under one watt [2.1]
- Adaptive motion estimation for efficient MPEG2 (MP@ML) video encoding [2.2]
- Very-low power (60mW) MPEG4 video codec using multiple supply voltages [2.4]
- Single-chip OFDM demodulator and channel decoder for digital terrestrial TV and digital-audio broadcasting [2.5, 2.6]
Session:
FA7 Subcommittee: Signal Processing
Low-Power and Signal-Processing Applications
Chair:
Wanda Gass, Texas Instruments, Dallas TX
Associate Chair:
Engel Roza, Philips Research Labs, Eindhoven, The Netherlands
DRIVERS
- Low-power implementations enable battery-operated systems
- Integration of digital and analog circuits gives single-chip solutions
- High resolution object detection
HIGHLIGHTS
- 5x reduction in power consumption for digital hearing aid [7.1]
- Energy-scalable encryption processor that can operate from 150uW to 150mW [7.2]
- 500uW video decoder for portable systems [7.3]
- Digital storage oscilloscope on-a-chip with Moire prevention [7.4]
- Fully-integrated system provides exhaustive audiometric tests [7.5]
- High-precision 2D convolution using 1024-point FFT processor [7.6]
Session:
SP24 Subcommittee: SIGNAL PROCESSING
Disk-Drive Signal Processing
Chair: Kaveh Parsi, Motorola Semiconductor, Inc., Tempe, Az.
Associate Chair:
Gregory Uehara, University of Hawaii, Honolulu, HI.
DRIVERS
- Higher storage densities
- Higher transfer rates
- Performance within package/power constraints
- Low cost
- High-volume manufacturability
HIGHLIGHTS
- Use of EPR4 for higher channel densities [24.1, 24.2, 24.5, 24.6, 24.8]
- Channel rates of 300Mb/s and above [24.1, 24.3]
- CMOS Multi-level Decision-Feedback Equalizer (MDFE) achieves 360Mb/s user data rate at 21mW [24.3]
- CMOS achieving speeds of 240Mb/s and above [24.3, 24.5, 24.6]
- High-integration implementations for DVD channels [24.4, 24.7]
Panel Session
: FE6 Subcommittee: Signal Processing
How Will Media Signal Processors Dominate the Next Decade?
OBJECTIVE
- Review trends in media signal processors
APPLICATIONS
- MPEG2 Video, 3D graphics, Dolby AC3 audio
CHALLENGES
- Fast arithmetic at low power
- High memory bandwidth
- Acceleration of IDCT and variable-length codes
CONTROVERSIES
- What is a media signal processor?
- Have DSPs won media processing from the host CPU and ASICs?
- Is silicon efficiency more important than compiler friendliness?
- Will PCs or consumer electronics be the most important application?
- How important are open software-development tools?
- What is the best architecture (VLIW, MP, SIMD, à)?
Tutorial:
T4 Subcommittee: Signal Processing
FIR-1001: Architectures and Applications
Mehdi Hatamian
OVERVIEW
- FIR filter architectures
- High-speed issues and pipelining techniques
- Adaptive filters and equalizers
- Applications in communication
TUTORIAL SPEAKER BIOGRAPHY
Mehdi Hatamian received the PhD in EE from the University of Michigan, Ann Arbor in 1982. From 1982 to 1991 he was with the Visual Communications Research and the VLSI Systems Research departments of AT&T Laboratories, where he became a Distinguished Member of Technical Staff in 1988. From 1991 to 1996 he was the Cofounder and Vice-President of Technology of Silicon Design Experts, Inc. In 1996 he joined Broadcom Corp. as Director of Digital Signal-Processing Microelectronics Technology. His interests are high-speed VLSI signal processing, full-custom design, adaptive filtering and high-density deep-sub-micron CMOS design.
Go back to the SSCS page
Go back to the ISSCC page
If you have any comments for the ISSCC, please forward them to
Frank Hewlett
hewletfw@sandia.gov
Comments related to the maintenance of this web site should be sent to
sscs@eecg.toronto.edu .
http://www.isscc.org/isscc/1998/press/signal.htm
Last modified : Tuesday February 17, 1998 at 8:12am EST