ISSCC 1998
Conference Overview


OVERVIEW

EVENTS

SHORT COURSE (Tuesday, February 3, 1998)

TUTORIALS (Wednesday, February 4, 1998)

WORKSHOP (Wednesday, February 4, 1998)

TECHNICAL SESSIONS (THURs. to SAT., February 5-7, 1998)

EVENING DISCUSSIONS (THURS., FRI., FEBRUARY 5-6, 1998)

SOCIAL HOUR (Thursday, February 5, 1998)

Plenary Session

[1.1] "Challenges in Semiconductor Technology for multi-megabit network services"

M. Nakamura, Hitachi Ltd., Japan

[1.2] "GSM AND BEYOND: THE FUTURE OF NETWORK ACCESS"

J. Danneels, Alcatel Semiconductor, Belgium

[1.3] "THE GLOBAL- POSITIONING SYSTEM: CHALLENGES IN BRINGING GPS TO MAINSTREAM CONSUMERS"

K. Chaddha, SiRF Technology, Sunnyvale, CA

PAPER STATISTICS

INTERNATIONAL SCOPE

  • Americas:;48 %
  • Far East:;34 %
  • Europe: ;18 %

COVERING A WIDE RANGE OF CIRCUIT SPECIALTIES

  • Analog 16 %
  • Communications 19 %
  • Digital 11 %
  • Memory 14 %
  • Sensors and Imagers 11 %
  • Signal Processing 14 %
  • Technology Directions 15 %

SESSION HIGHLIGHTS

ANALOG [TP4, FA9, FP14, SA20]:

Communications [TP3, FA8, FP13, SA19, SP23]:

  • Portable RF Data Systems [TP3]
  • RF Chips Allow Consumer Products To Make Better Use of Global Information Resources [FA8]
  • Local-Area Networks and Routers Become Faster and More Efficient [FP13]
  • Backbone Links Move to Multi-Gigabit Speeds [SA19]
  • Circuit Techniques for Higher-Level Integration [SP23]

DIGITAL [FA10, FP15, SA18, SP25]:

  • Next-Generation x86 Microprocessor Designs [FP15]
  • Architecture, Circuits, and Process Technology for 1GHz CMOS Microprocessors [FP15, SP25]
  • Microprocessors for Media-Intensive Embedded Applications [SA18]

Memory [TP5, SA21, SP22]:

  • Gigabit DRAM Optimized for Low Power [TP5]
  • Embedded DRAM with Integrated Graphics-Controller Engine [SA21]
  • 128Mb Single-Electron-Memory Prototype [SA21]
  • High-Bandwidth SRAMs (over 500MB/s) [SP22]

SENSORS and IMAGERS [FA11, SA17)]:

  • A Renewed Interest in Image Sensors Shows Innovative Chips With Smaller Pixels, Higher Resolution, and Higher Systems Integration [FA11]
  • A Microchip-Based DNA Array [SA17]
  • A Universal Sensor/Transducer Interface on a Single Chip [SA17]

SIGNAL PROCESSING [TP2, FA7, SP24]:

  • Video and Multimedia Processors [TP2]
  • Low-Power Signal Processing [FA7]
  • Disk-Drive Signal Processing [SP24]

TECHNOLOGY DIRECTIONS [TP6, FP12, FP16]:

  • Processor Architectures, Deep Submicron Circuits and Optical Interconnects for Future Generation Computers [TP6]
  • Low Power / Low Voltage Analog and Digital Circuits [FP12]
  • Advanced RF Circuits [FP16]

Overseas Panel: Europe

Sub-1V CMOS: SOI or BULK?

OBJECTIVE
  • To determine whether CMOS will be bulk or SOI below 1V

APPLICATIONS

  • Low-voltage digital circuits

CHALLENGES

  • SOI wafer cost
  • SOI production level

CONTROVERSIES

  • Power versus cost
  • Functional density
  • Process complexity

Overseas Panel: Far East

LSI Solutions and enabling technologies for mobile multimedia devices at the year 2002

OBJECTIVE
  • To propose optimum LSI solutions for handheld devices

APPLICATIONS

  • Mobile Multimedia Devices

CHALLENGES

  • Determine which functions are essential
  • Determine which functions should be on-chip

CONTROVERSIES

  • Which system will win: PC, PDA, or next-generation digital cellular?
  • What is the best digital core: media processor, microprocessor, DSP, or dedicated hardware?
  • Can analog live with 1.2V, 0.1 micron digital CMOS on the same die?

Short Course:

xDSL broadband interactive communications via pots

Time: Tuesday preceding the Conference: February 3, 1998

Session I: Course 8:00 AM-4:30 PM

Session II: Course 10:00 AM-6:30 PM

Session III: Course 1:00 PM-9:30 PM

Course Objective:

This short course on advanced digital subscriber loop (xDSL) communications over the twisted-pair copper infrastructure existing in the plain old telephone system (POTS) requires no prior knowledge of the subject. Course completion provides an overall perspective and a detailed introduction to circuit design and system specification of xDSL modems, including architecture, technology, and analog/digital circuit tradeoffs in high-speed digital subscriber loop (HDSL), asymmetric digital subscriber loop (ADSL), and very-high-speed digital subscriber-line (VDSL) systems.

Lecturers:

  • J. Bingham, Amati Communications Corporation
  • D. Johns, University of Toronto
  • D. Macq, Alcatel Mietec
  • J. Cioffi, Stanford University

Course Outline:

High-Speed Data on the Subscriber Loop: xDSL (Bingham)
transmission media and unique impairments, methods for overcoming the impairments of DSL systems

Passband HDSL and ADSL Circuits and Systems (Johns)
basics of CAP and QAM signaling, circuit-design challenges for HDSL and ADSL systems

DMT ADSL Circuits and Systems (Macq)
requirements for integration of FDM or EC DMT ASDL systems, implementations for AD, DA and continuous-time filters and drivers, comparison of various DSP architectures

Very-High-Speed Digital Subscriber Lines (Cioffi)
VDSL description, fiber-to-the-node architecture of asymmetric and symmetric full-service access networks

TUTORIALS:

T1 HIGH-SPEED SRAM DESIGN (B. Bateman, MicroUnity System Engineering)

T2 HOW A SPREAD-SPECTRUM RADIO WORKS (C. Chien, Rockwell Science Center)

T3 OPAMP COMPENSATION FOR LOW-VOLTAGE MIXED-SIGNAL DESIGNS (J. Fattaruso, Texas Instruments)

T4 FIR-1001: ARCHITECTURES AND APPLICATIONS (M. Hatamian, Broadcom Corporation)

T5 MEMS FOR THE CIRCUIT DESIGNER (K. Najafi, University of Michigan, and W. Kaiser, UCLA)

T6 HIGH-SPEED CLOCKING FOR LARGE DIGITAL ICS (J. Maneatis, Silicon Graphics)

Go back to the SSCS page

Go back to the ISSCC page

If you have any comments for the ISSCC, please forward them to

Frank Hewlett
hewletfw@sandia.gov

Comments related to the maintenance of this web site should be sent to sscs@eecg.toronto.edu .

http://www.isscc.org/isscc/1998/press/overview.htm
Last modified : Tuesday February 17, 1998 at 8:12am EST