MEMORY
- Daytime Paper Sessions
- Evening Panel Discussion
- Tutorial
- Trend Charts
1998 ISSCC - MEMORY
Subcommittee Chair:
Richard Crisp, Rambus Inc., Mountain View, CA.
HIGHLIGHTS
- Gigabit DRAM optimized for low power [TP5]
- Embedded DRAM with integrated Graphics Controller Engine [SA21]
- 128Mbit Single-Electron-Memory Prototype [SA21]
- Several High-Bandwidth SRAMs (over 500MB/s) [SP22]
MOST-SIGNIFICANT RESULTS
- Ground-level precharge implemented with a non-boosted word line in a 1Gb SDRAM [5.6]
- Graphics Controller using DRAM with which processing elements are embedded to attain 33GB/s bandwidth [21.5]
- 1.8ns access time 4.5Mb SRAM with 2.8W dissipation [22.7]
APPLICATIONS
- High-performance battery-powered devices [5.6]
- High-performance portable-computing display controllers [21.5]
- High-performance L1/L2 Caches [22.6]
ECONOMIC AND SOCIAL IMPACT
- Enhanced density with reduced power at higher speed as a result of advanced DRAM development
- Improved cache transfer rate and access time well-matched to requirements of modern high-performance microprocessors
- Cost, power and physical-size reduction attained for portable computing applications
PANEL
- Three Decades of DRAM Development, Debate and Distinction [TE1]
TUTORIAL
- High-Speed SRAM Design [T1]
Session:
TP5 Subcommittee: MEMORY
DRAM
Chair:
Tohru Furuyama, Toshiba Corp., Kawasaki, Japan.
Associate Chair:
Peter Gillingham, MOSAID Technologies, Carp, Ontario, Canada.
DRIVERS
- Fast Turn-Around-Time (TAT) for embedded DRAM design
- High bandwidth for both embedded and stand-alone DRAM
- Low power consumption
- Die-size reduction and yield improvement for high density DRAM
HIGHLIGHTS
- Highly flexible embedded DRAM macrocells providing capacities ranging from 0.5Mb to 32Mb. [5.1, 5.2]
- High bandwidth embedded DRAM with 128bit and 256bit interfaces, operating from up to 150MHz. [5.1, 5.2]
- New differential-bus circuit technique increases internal DRAM datarate to 500Mb/s. [5.3]
- Redundancy architecture repairing up to 1400 faults for improved yield. [5.4]
- 256Mb and 1Gb DRAM die sizes reduced to 200mm2 and 500mm2 respectively. [5.4, 5.5, 5.6]
- Subthreshold leakage-current-supression technique for low standby power. [5.5]
- Reliability improvement by eliminating boosted wordline voltage. [5.6]
Session:
SA21 Subcommittee: Memory
MEMORY: NONVOLATILE AND EMBEDDED
Chair:
T-S. Jung, Samsung Electronics Co., Ltd., Yong-in, Kyungki-do, Korea.
Associate Chair:
T-S. Feng, United Microelectronics Corp., Hsinchu, Taiwan.
DRIVERS
- Integration of Logic and Memory
- Higher graphics-subsystem performance
- Higher number of bits stored in a single cell
- Higher density
HIGHLIGHTS
- Largest (64k x 40) fully-parallel CAM reported uses NAND match-line chains [21.1]
- Analog techniques for up to 8 bits/cell nonvolatile storage [21.2, 21.3]
- 133MHz 32Mb synchronous mask ROM can sit on a DRAM bus [21.4]
- Integration of Logic and DRAM for improved graphics performance [21.5, 21.6]
- 128Mb single-electron memory prototype [21.7]
Session:
SP22 Subcommittee: MEMORY
SRAM
Chair:
Koichiro Ishibashi, Hitachi Ltd., Tokyo, Japan
Associate Chair:
Tomohisa Wada, Mitsubishi Electric Corp., Hyogo, Japan
DRIVERS
- High frequency, high bandwidth for L2 cache in systems
- Special-purpose embedded memories that enhance CPU performance
- Low-power, low-voltage operation for mobile applications
HIGHLIGHTS
- New functional-cache memories for high-speed CPUs [22.1, 22.2]
- A bipolar merged memory cell for 3.6mW, 1.4V operation [22.3]
- A Half-Swing Decoder SRAM operating at 1V and 0.9mW [22.4]
- 400MHz to 800MHz frequency, 4Mbit SRAMs for L2 cache [22.5, 22.6, 22.7]
Panel Session:
TE1 Subcommittee: Memory
Three Decades of DRAM Development, Debate, and Distinction
OBJECTIVE
- The panel experts and audience will review the history of DRAM development
APPLICATIONS
CHALLENGES
- Identify the ten most-significant innovations
- Speculate on improvements yet to come
CONTROVERSIES
What was the context surrounding each development?
What was the reason for its significance?
When and where was it first used?
Who was (were) its inventor(s)?
Tutorial
: T1 Subcommittee: Memory
High-Speed SRAM Design
Bruce Bateman
OVERVIEW
- Architectures: sub-arrays, aspect ratio, data busing
- High-Speed Circuits: Optimum fanout, decoders, sense amps
- Memory Cell Types: # transistors, # ports, stability
- Asynchronous vs Synchronous design
TUTORIAL SPEAKER BIOGRAPHY
Bruce Bateman received the BS in EE/Materials Science & Engineering from UC Berkeley in 1976 and has been involved in memory design, primarily in high-performance SRAMs and technology development. He was Manager of the SRAM design group at Cypress Semiconductor from 1983 through 1989 and has been involved in high-performance embedded memory at MicroUnity and SGI since 1992. He is currently Director of VLSI Design at MicroUnity Systems Engineering.
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