MOST-SIGNIFICANT RESULTS

• First demonstration of a 1GHz microprocessor [15.1]
• First microprocessor with copper interconnect [15.6]
• First dynamic multi-threaded microprocessor [15.3]
• Third-generation 450MHz P6 microprocessor [15.4]
• 667MHz commercial microprocessor [18.4]
• 800Mbit/s per pin interface to high-density memories [10.1, 10.4]
• 1.2GHz phase-locked loop for a 600MHz Alpha microprocessor [25.2]
• Low-skew GHz clock distribution schemes [25.3, 25.4, 25.5
• MPEG2 (ML@MP) decoding in software at 1.2W [18.2, 18.6]

APPLICATIONS

• High-Performance Personal Computing and Servers [FA10, FP15, SP25]
• Higher-Performance, Lower Power, Portable Computing [FP15, SA18]
• Portable and Embedded Multimedia [SA18]
  • PDAs [18.3]
  • Video-on-demand set-top boxes [18.6]

ECONOMIC AND SOCIAL IMPACT

• Increased use of digital audio, graphics, and video content in daily life
• Improved human interface - handwriting and speech recognition
• Business productivity
• Flexible work environment / telecommuting

PANEL

• Will Power Limit Microprocessor Performance? [TE4]

TUTORIAL

• High-Speed Clocking for Large Digital ICS [T6]

• Background
  • Deep sub-micron interconnect is becoming increasingly resistive due to very narrow wires with larger R
  • Coupling capacitance to adjacent wires is increasing due to narrow spacing between wires with larger C
  • RC wire delays do not scale well with shrinking dimensions
  • Copper has 40% lower resistance than Aluminum leading to reduced RC wire delays

• Challenges
  • Copper interconnect is difficult to manufacture. It requires barrier layers to stop copper diffusing into the silicon. It is difficult to pattern. These problems have now been overcome.
  • Copper interconnect will pose a challenge for further reducing RC delay. Thinner barrier layers and low-k dielectrics will be the next challenges

• Multi-threading is a technique for improving computer performance.
• There are several different ways to do this, either in software or in hardware, either course-grain or fine-grain.
  • This year ISSCC has a paper describing the first microprocessor implementing a mainstream architecture (the PowerPC) with course-grain multithreading.
• Course-grain multithreading hides the delays caused by data fetches from memory by switching between 2 or more program threads.
  • When required data is not found in the on-chip cache, the processor will start fetching instructions from a new thread.
  • Otherwise-idle processor cycles can now be filled with useful computation, thus improving performance

DRIVERS

• Higher bandwidth for increased throughput
• Lower power for reduced system cost

HIGHLIGHTS

• 800Mb/s per pin interface [10.1, 10.4]
• Data driven on both clock edges [10.1, 10.4]
• Comparison of competing standards:
  • Data synchronized to master clock [10.1, 10.4, 10.5]
  • Clock/strobe sourced with data [10.2, 10.3]
• 320Mb/s per pin interface [10.2]
• 600Mb/s per pin interface [10.3]
• 1Gb/s at 10mW per pin interface [10.5]
• Low-skew global clock-distribution scheme [10.5]

DRIVERS

• General-purpose computing
• Low-power-portable computers
• Personal Computers
• Workstations

HIGHLIGHTS

• First demonstration of a 1GHz microprocessor [15.1]
• 600MHz out-of-order instruction-queue circuit [15.2]
• First multi-threaded PowerPC microprocessor [15.3]
• Third-Generation 450MHz Intel P6 microprocessor [15.4]
• Highly-integrated low-power 200MHz, 0.5W Strong Arm microprocessor [15.5]
• First microprocessor with copper interconnect [15.6]
• 0.25micron AMD K6 microprocessor with 100MHz socket 7 [15.7]

DRIVERS

• Low Power for Portable and Embedded Applications
• Flexible Software-based Processing
• High-Performance Arithmetic
• Multiple Forms of Parallelism for Multimedia

HIGHLIGHTS

• 1.4GFLOP processor with graphics vector-floating-point unit [18.1]
• MPEG2 (ML@MP) decoding in software at 1.2W [18.2,18.6]
• 110mW, 1.5V, 4-way-parallel DSP for portable multimedia [18.3]
• Fastest commercial microprocessor : 667MHz [18.4]
• 2.7ns multiplier array for a 400MHz FPU [18.5]

DRIVERS

• GHz clock distribution
• Phase-locked loops (PLL)
• Delay-locked loops (DLL)
• High frequency
• Low jitter
• Low skew
• Skew immunity
• Race-free operation

HIGHLIGHTS

• 1.2GHz phase-locked loop for a 600MHz Alpha microprocessor [25.1]
• Clock design for a 600MHz Alpha microprocessor [25.2]
• Low-skew GHz clock distribution schemes [25.3, 25.4, 25.5]
• Clock distribution network for a 450MHz P6 [25.3]
• Race-free impulse latch circuits [25.4]