ANALOG
- Daytime Paper Sessions
- Evening Panel Discussion
- Tutorial
1998 ISSCC - ANALOG
Subcommittee Chair:
Behzad Razavi, UCLA, Los Angles, CA.
HIGHLIGHTS
- Breakthroughs in Low-Voltage and Low-Power SD Modulators [TP4]
- High-Speed ADCs for Disk-Drive Applications [FA9]
- High-Speed High-Resolution CMOS DACs [FP14]
- High-Speed Low-Distortion Line Drivers [SA20]
MOST-SIGNIFICANT RESULTS
- 900mV SD Modulator with 77dB Dynamic Range and 40uW Power [4.6]
- 400MS/s 6-Bit CMOS ADCs [9.7, 9.8]
- 10-Bit 250MS/s CMOS DAC [14.1]
APPLICATIONS
- Low-Power One-Battery Portable Systems [4.2, 4.6]
- Disk Drives, Data Communications (ADSL) [9.1, 9.7, 9.8]
- Wireless Transceivers [14.4]
ECONOMIC AND SOCIAL IMPACT
- Affordable Mobile Computing and Communication
- High-Speed Data Transfer in Local and Wide-Area Networks
- Low-Cost High-Density Disk Storage
PANEL
- How Much Analog Will Survive On Digital Circuits? [TE2]
TUTORIAL
- Op-Amp Compensation for Low-Voltage Mixed-Signal Designs [T3]
Session:
TP4
Subcommittee: Analog
Oversampling Converters
Chair: Donald Kerth, Crystal Semiconductor, Austin, TX.
Associate Chair:
Stephen Lewis, University of California, Davis, CA.
DRIVERS
- Low-Power and Low-Supply Operation
- High-Quality Audio
- Digital Radio Communications
HIGHLIGHTS
- Dynamic Element Matching for Improved Linearity [4.1,4.2,4.3,4.4]
- High Dynamic Range, 113dB [4.3]
- Less than 1V Supply Operation [4.6]
Session:
FA9 Subcommittee: Analog
ADCs
Chair: Bob Jewett, Hewlett-Packard Labs, Palo Alto, CA.
Associate Chair: Klaas Bult, Broadcom Corporation Irvine, CA.
DRIVERS
- Disk-drive read back
- DVD
- LAN Receivers
- ADSL
- Cellular base stations
HIGHLIGHTS
- Self-calibrating ADCs [9.1, 9.2, 9.3, 9.4]
- Low-power (70mW) 75MS/s ADC [9.5]
- Fast (150MS/s to 400MS/s) CMOS ADCs [9.6, 9.7, 9.8]
Session:
FP14 Subcommittee: Analog
ANALOG TECHNIQUES
Chair:
Paul Brokaw, Analog Devices, Wilmington, MA.
Associate Chair:
Hae-Seung Lee, MIT, Cambridge, MA.
DRIVERS
- Current Steering for Speed (DACs)
- CMOS for Compatibility and Low Cost (DACs)
- Error-Reducing Layout Techniques (DACs)
- Tuning for Integrability (Filters)
- On-chip Inductors for Integrability, Low Cost, and High Frequency (VCOs)
- Extended-Frequency Operation (VCOs)
- Low Phase Noise for DECT (VCOs)
HIGHLIGHTS
- 10b, 250MS/s in 1mm2 CMOS [14.1]
- 12b, 300MS/s in 3.2mm2 CMOS [14.2]
- 10.7MHz-Q Tuned to 20 with Less Than 1% Error [14.3]
- 49dBm IIP3 Above 200kHz Passband with 2.7V Supply [14.4]
- 20MHz to 800MHz Tuning Range [14.5]
- 2GHz VCO with û136dBc/Hz at 4.7MHz Offset [14.6]
- 5GHz, 2.7V VCO [14.7]
Session:
SA20 Subcommittee: ANALOG
Amplifiers
Chair:
Tsutomu Wakimoto, NTT, Kanagawa, Japan.
Associate Chair:
Geert De Veirman, Silicon Systems, Tustin, CA.
DRIVERS
- Adaptive impedance matching
- High accuracy and stability
- Low drift and jitter
- High-speed measurement
HIGHLIGHTS
- Adaptive impedance-matching video line-driver for 38 Ohm to 85 Ohm loads[20.1]
- Low-distortion line-driver for Fast Ethernet [20.2]
- 10ppm/year drift up to 225oC instrumentation amplifier [20.3]
- High-swing CMOS telescopic opamp [20.4]
- 7.2o jitter AM-supression CMOS AGC [20.5]
- 5GS/s track-and-hold and 3GS/s quasi-sample-and-hold [20.6]
Panel Session:TE2 Subcommittee: Analog
How much Analog is going to survive on large digital chips?
OBJECTIVE
- To determine if high-performance analog-circuit designs will be part of large digital systems ICs
APPLICATIONS
CHALLENGES
- How to design high-performance analog circuits with a low supply voltage and in the presence of cross-talk
- How to deal with process choice, design time, and yield
CONTROVERSIES
- Will multi-chip solutions be needed?
- Will there be special process options to comply with analog needs?
- Must circuit solutions be invented to solve problems?
Tutorial
: T3 Subcommittee: Analog
Opamp Compensation for Low-Voltage, Mixed-Signal Designs
John W. Fattaruso
OVERVIEW
- Motivation for high-speed, multistage, low-supply-voltage opamps
- Design issues and circuit topologies
- Detailed multistage compensation techniques: review of pole-splitting, nested Miller compensation, nested Gm-C compensation, other recent developments.
- Practical CMOS design examples
TUTORIAL SPEAKER BIOGRAPHY
John W. Fattaruso
received the Ph.D. in EE from UC Berkeley in 1987. He has since worked in CMOS analog-circuit R&D at Texas Instruments in Dallas, where he was elected Senior Member of Technical Staff in 1994. He currently holds 10 patents in circuit design, and has authored or co-authored 16 journal and conference papers.
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