Toshiba Corp., Yokohama, Japan
1 Information Systems (Japan) Corp., Kawasaki, Japan
A DRAM macro design enables 2112 configurations up to a maximum capacity of 32Mb with 288b I/O. The macro size is comparable to that of manually-designed DRAM. An expandable redundancy and memory array architecture is proposed as well as a unified macro testing scheme using 33 pads. A 4Mb-DRAM-embedded chip and an 8Mb-DRAM test chip showing 150MHz operation use 0.35um technology.
IBM Microelectronics Div., Essex Junction, VT
A granular DRAM macro provides 0.5 to 8.0MB configurations with 128b or 256b interface for use as an ASIC library macro. A processor-based BIST engine for DRAM test includes two-dimensional redundancy calculation and allocation and in-situ burn-in. Level-sensitive-scan design techniques allow full test of the BIST prior to DRAM test. A range of macrocells have been verified in 0.45um trench technology.
Fujitsu Laboratories, Ltd., Nakahara, Japan
Differential partial-response detection permits use of a non-precharged bus to increase DRAM core bandwidth. Read databus bandwidth is increased to 500Mb/s, 2.5 times that of a conventional DRAM core. The technique is verified in a 4Mb test chip using 0.24um technology.
IBM/Siemens/Toshiba at IBM, Hopewell Junction, NY
A 220mm2 4 and 8 bank 256Mb SDRAM uses 0.22um CMOS. Single-sided stitched WL architecture employs asymmetric block activation, and realizes 86.7% cell/chip-length efficiency. An intra-unit address increment pipeline with single-ended RWDs results in 13.5ns tAC1, and 4ns tCK5 (250MHz). Selectable row domain and divided column redundancy repairs ~1400 faults/chip.
Hitachi Ltd., Device Dev. Center Tokyo
1Hitachi Ltd., Semiconductor & Integrated Circuits Div., Tokyo
2Hitachi Device Eng. Co. Ltd., Chiba
3Hitachi ULSI Eng. Corp., Tokyo, Japan
A 204.9mm2 256Mb 167MHz SDRAM has 29ns RAS access and 1ns clock access. Low Vth high-driveability MOSFETs, combined with subthreshold leakage current suppression reduce standby current to 200mA. A 64-cycle lock-in 0.1ns resolution delay-locked-loop (DLL) uses successive approximation.
Fujitsu Ltd., Kawasaki
1Fujitsu VLSI, Ltd., Japan
A 1Gb SDRAM uses a ground-level-prechanged bit line enabling a non-boosted word-line architecture, reducing overall row power. A Vernier-type DLL circuit realizes ˜20ps quantization errors for clock recovery and skew elimination. The 505mm2 die uses 0.18um technology.
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