SESSION TP4

SALON 8

OVERSAMPLING CONVERTERS

Chair: D. Kerth, Crystal Semiconductor, Austin, TX
Associate Chair: S. Lewis, Univ. of California, Davis, CA

4.1 - An Audio DAC with 90dB Linearity using MOS to Metal-Metal Charge Transfer - 1:30 PM

L. Williams, III

Texas Instruments, Dallas, TX

An audio DAC has a signal-to-distortion ratio better than 90dB. A multi-level SD modulator drives a switched-capacitor filter using charge transfer between dense MOS capacitors and linear metal-metal capacitors. The active area is 1.8mm² in 0.5um. The chip consumes 47mW from 3.3V

4.2 - A 1.5V 4.1mW Dual-Channel Audio DS D/A Converter - 2:00 PM

I. Fujimori, T. Sugimoto

Asahi-Kasei Microsystems, Kanagawa, Japan

A stereo DAC for portable audio operates at 1.5V and consumes 4.1mW. The 15-level, 3rd order SD DAC employs data weighted averaging and a direct charge transfer SC-DAC for power reduction. The DAC achieves 90dB audio-band dynamic range. The 0.6um low-threshold CMOS chip requires 5.3mm².

4.3 - A 113dB SNR Oversampling DAC with Segmented Noise-Shaped Scrambling - 2:30 PM

R. Adams, K. Nguyen, K. Sweetland

Analog Devices, Wilmington, MA

A SD D/A converter in 0.6um CMOS uses a 6b modulator and segmented noise-shaped scrambling for 113dB dynamic range over a 20kHz bandwidth. A continuous-time output stage achieves high SNR in 3.2x3.1mm². The output stage uses a dual return-to-zero circuit that eliminates errors caused by intersymbol interference.

BREAK 3:00 PM

4.4 - A 100kHz, 9.6mW Multi-bit DS DAC and ADC using Noise Shaping Dynamic Element Matching with a Tree Structure - 3:15 PM

A. Yasuda, H. Tanimoto, T. Iida

Toshiba Corp., Saiwai-ku, Japan

Multi-bit 3rd-order DS ADC and DAC with noise shaping dynamic element matching techniques use a tree structure. They achieve dynamic ranges of 80dB (DAC) and 79dB (ADC) within a 100kHz bandwidth using a 5MHz clock. The 4x6mm², 0.6um CMOS device consumes 9.6mW (DAC), 5.2mW (ADC) at 2.7V.

4.5 - Paper withdrawn by the authors - 3:45 PM

4.6 - A 900mV 40mW Switched Opamp DS Modulator with 77dB Dymanic Range - 4:15 PM

V. Peluso, P. Vancorenland, A. Marques, M. Steyaert, W. Sansen

Katholieke Universiteit Leuven, Leuven, Belgium

A 40mW 3rd-order DS ADC in a 0.5um standard CMOS uses a 900mV supply. The DAC uses no voltage multiplication or low-Vt transistors. The ADC achieves 77dB dynamic range in 16kHz bandwidth with a differential switched opamp implementation, a class AB OTA and a DS topology employing half-delay integrators.

CONCLUSION 4:45 PM

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