CSEM, Neuchatel, Switzerland
A clock generator has reference frequency range of 45-250MHz and VCO frequency between 0.35-2.3GHz. It is integrated with an Alpha processor in a 0.35um CMOS process. The cycle-to-cycle jitter is < +/- 20ps with 200mV supply step. Peak time misalignment between phase-and-frequency detector inputs is <300ps. The output frequency can be changed by steps instantaneously with limited overshoot.
Digital Semiconductor, Hudson, MA
The hierarchical clock design methodology for a 600MHz Alpha microprocessor and the two analysis methods used to verify it are described. One analysis approach is a traditional AWESIM-based method for the global clocks. The other is a worst-case SPICE-based network simulation technique for the numerous smaller clocks.
Intel Corporation, Hillsboro, OR
An active digital deskewing circuit for clock network distribution in a 450MHz P6 microprocessor uses digital delay lines, a phase detection circuit, and a controller to equalize two clock distribution spines. The skew between two spines from device and load mismatches as well as voltage and temperature gradient effects is limited to 15ps.
NEC Corp., Kanagawa, Japan
A ring-type clock distribution network and skew-immune race-free impulse latches achieve synchronization above 1GHz with 50ps global clock skew in 0.18um CMOS.
Hitachi, Ltd., Central Research Labs., Tokyo, Japan
A GHz clock distribution network uses distributed VCOs in a matrix configuration oscillating in phase at the same frequency. Estimated increases of skew and jitter in 0.25um 1.8V CMOS are less than 39ps and 14ps, respectively, with local 180mV supply step or ˜0.1V threshold voltage variation.
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