1Siemens AG, Muenchen, Germany
2AEG Mobile Communications GmbH, Ulm, Germany
A transmitter IC implements quadrature modulation with a phase-locked loop. The IC contains a mixer, a modulator, two programmable counters and a phase detector. With external 900MHz VCO and LC/RC filters, the loop achieves a phase error of 1.5o rms. and -166dBc/Hz phase noise at 20MHz offset.
University of California at San Diego, CA
1Istituto di Elettronica, Universita di Perugia, Italy
2Newport Microsystems, Irvine, CA
A DSPLL demodulates and digitizes a 10MHz FM signal at 50kSample/s. The 0.6um CMOS chip achieves a worst-case SINAD and SFDR of 85.1dB and 88.1dB, respectively. The 4mm2 chip dissipates 35mW from a 5V supply.
Toshiba Corp., Kawasaki, Japan
A 1.9GHz direct downconverter in 13GHz BiCMOS contains two active balanced harmonic mixers, a 45o phase shifter, and two 3b DACs for IM2 cancellation. The chip dissipates 184mW and achieves +37dBm IIP2.
Bell Labs., Lucent Technologies, Murray Hill, NJ
A mixer circuit uses an LO connected to the backgate to allow 1V operatiuon with <0.2mW power dissipation. Measured results include 6dB gain, 9.6dB noise figure, and 10dBm IIP3 at 2GHz, and 6dB gain, 18dB noise figure, and -2dBm IIP3 at 7GHz.
Katholieke Universiteit Leuven, Heverlee, Belgium
A 1702.4MHz-to-1888.6MHz frequency synthesizer in standard 0.4um CMOS uses no external components. The 4th-order, type-2 charge pump PLL integrates a hollow-coil inductor VCO and a dual-path active loop filter on a 3.2mm2 die. Settling time is 300ms and phase noise is -121dBc/Hz at 600kHz offset.
NEC Corp., C&C Media Res. Labs., Kawasaki, Japan
1NEC Corp., ULSI Device Dev. Lab., Sagamihara, Japan
A 5GHz up/down-converter IC with a single 2.6-5.2V bias voltage uses 0.4um BiCMOS. The 7.2mm2 die dissipates 56mW in receive mode and 66mW in transmit mode. The receiver has 7dB noise figure and 2dBm IIP3.
Go back to Table of Contents