Nortel Semiconductors, Ottawa, Ontario, Canada
A 25MHz 64kx40 CAM, the largest fully-parallel CAM to date, employs NAND match line chains for low power, and two chains per word for speed. A word-sliced architecture is augmented by operation-specific self-timing loops. The 230mm2 7.5W chip in 5-metal 0.35um CMOS, incorporates BIST and is cascadable.
SGS-Thomson Microelectronics, Agrate Brianza, (MI), Italy
A 1M-cell memory prototype for non-volatile digital storage achieves up to 6b per cell (equivalent of 6Mb). The chip, suitable for applications such as digital still camera, stores 24VGA full-color JPEG images or 40 minutes of compressed speech. The chip uses standard 3V 0.5um Flash-EEPROM process with 2-poly 2-metal. Array density is 257Mb/cm2.
Korea Advanced Institute of Science and Technology, Taejeon, Korea
An EEPROM programing scheme is based on a nonvolatile analog memory (NVAM). Constant programming rate with single program pulse drastically enhances programming speed and accuracy. A test chip containing 8x128 NVAM cells (9x13.6um2 cell) is fabricated using 0.8um CMOS. Each cell stores 8b in 360us.
Samsung Electronics, Ltd., Kiheung, Korea
A 32Mb mask ROM has SDRAM-compatible interface and control. Using time-multiplexed page sensing and dynamic load with mirror bias sense amplifier, 133MHz operation is obtained with single-metal 0.4um CMOS. The die is 62.45mm2. The typical data access time is 5.8ns.
MOSAID Technologies,Inc., Carp, Ontario, Canada
1Accelerix Inc., Ottawa, Ontario, Canada
2Symbionics Ltd., Cambridge, England, UK
A complete PC graphics system including the DRAM frame buffer, implemented in a 0.35um/0.5um merged DRAM/logic process, is integrated on a 129mm2 die. The frame buffer includes 13.4Mb DRAM, with 4kb wide I/O port, 3 4kb-wide serial output registers, and 4kb-wide SIMD processor that allows 4kb wide graphics rastor operations. Registers and processor are pitch-matched to the DRAM, allowing 33GB/s bandwidth between pixel processor and DRAM.
NEC Corp., Sagamihara, Japan
1NEC Informatec Systems., Ltd., Kanagawa, Japan
A CompressDRAM integrates compression/decompression hardware into a packet-oriented DRAM. By embedding this chip in a unified memory system, graphics-related memory bus traffic is reduced from 90% to 50%. A 16Mb prototype integrates a 200MHz compressor/decompressor with 800MB/s Synclink-type DRAM I/F using a 0.35um merged logic-DRAM process.
1Hitachi Device Engineering, Kokubunji, Tokyo, Japan
Large-scale integration of the single-electron memory targets minimum bit-cost using double-stacked 2F2/bit-cell. The cell-to-cell variations of characteristics that make large-scale integration difficult are compensated for by dummy-cell-referenced verified read/write. The cell is 0.145um2/b using 0.25um technology.
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