Katholieke Universiteit Leuven, Heverlee, Belgium
The potential of supply voltages down to 1V for analog integrated circuits in standard CMOS is investigated. Voltage multipliers or reduced threshold voltages are not considered. Low supply voltage does not necessarily lead to power reduction. This is illustrated by circuit techniques and realizations such as rail-to-rail input, pseudo-differential and current differential stages.
Mitsubishi Electric Corp., Hyogo, Japan
An 8b multiplexer and an 8b demulitplexer are based on a 0.32um gate array technology with regular-structured dynamic-threshold voltage CMOS/SOI. At 0.5V, the multiplexer, using the optimized flip-flop circuits for SOI structures, operates at 320MHz with 2.0mW, and the demultiplexer operates at 380MHz with 1.4mW.
NTT System Electronics Laboratories, Kanagawa, Japan
A triple-threshold CMOS/SIMOX circuit reducing active and standby current requires no additional masks or process steps. Fully-depleted SIMOX devices with small sub-threshold swings permit use of low-Vth MOSFETs in critical paths and medium-Vth MOSFETs in non-critical paths. An experimental 16b adder reduces active power dissipation by >60% while maintaining 5ns delay time at 0.5V and 2ns at 1.0V.
University of Tokyo, Tokyo, Japan
Inserting a low-Vth MOSFET whose gate is over driven in standby in series to a low-Vth circuit block enables 0.6ns fanout 3 inverter operation at 0.5V VDD and achieves pA-level leakage in a standby mode. Flip-flop operation is experimentally verified.
Tohoku University, Sendai, Japan
A logic-in-memory VLSI architecture merges storage and switching in a multiple-valued-input and binary-output combinational logic circuit that realizes parallel arithmetic and logic. Multiple-valued stored data are represented by the threshold voltage of a floating-gate MOS transistor, so both multiple-valued threshold-literal and pass switch functions can be merged using a single floating-gate MOS transistor for parallelism as well as compactness.
SGS-Thomson Microelectronics, Berkeley, CA
A 2-D image convolver chip uses multi-level storage on pairs of Flash cells to compute dot-product in analog. The chip contains 512k conductance-mode computing nodes, organized into 256 rows of 2k synapses each and achieves 23GCPS/mW computing efficiency. Real-time filtering for road-boundary detection is performed.
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