SESSION FA9

SALON 8

ADCs

Chair: B. Jewett, Hewlett Packard Labs, Palo Alto, CA
Associate Chair: K. Bult, Broadcom Corporation, Irvine, CA

9.1 - A Single-Ended 12b 20MSample/s Self-Calibrating Pipeline A/D Converter - 8:30 AM

I. Opris, L. Lewicki, B. Wong

National Semiconductor, Santa Clara, CA

A single-ended 12b, 20MSample/s, self-calibrating, pipeline A/D converter in 0.7um CMOS is 3.2x3.1mm2 and dissipates 250mW from a single 5V supply. Linearity is improved through self-calibration and digital correction with on- chip circuitry.

9.2 - Digital Background Calibration of a 10b 40MSample/s Parallel Pipelined ADC - 9:00 AM

D. Fu, K. Dyer, S. Lewis, P. Hurst

Univ. of California at Davis, CA

Digital calibration using adaptive signal processing and extra resolution matches offsets and gains of time-interleaved channels in a 10b 40MSample/s pipelined ADC. With monolithic background calibration, peak SNDR is 55db, and power dissipation is 565mW from 5V. The active area is 42mm2 in 1um CMOS.

9.3 - Analog Background Calibration of a 10b 40MSample/s Parallel Pipelined ADC - 9:30 AM

K. Dyer, D. Fu, S. Lewis, P. Hurst

Univ. of California at Davis, CA

Analog background calibration using adaptive signal processing, an extra channel, and mixed-signal integrators matches the offsets and gains of time-interleaved channels in a 10b 40MSample/s pipelined ADC. With monolithic background calibration, peak SNDR is 58dB, and power dissipation is 650mW from 5V. Active area is 47mm2 in 1um CMOS.

BREAK 10:00 AM

9.4 - A Continuously-Calibrated 10MSample/s 12b 3.3V ADC - 10:15 AM

J. Ingino, Jr., B. Wooley

Stanford Univ., Stanford, CA

A 12b, 10MSample/s, 3.3V pipelined A/D converter incorporates a continuous analog calibration to perform corrections without high-linearity hardware or complex signal processing. Measured peak SNDR is 67dB for a 497kHz input. Power dissipation is approximately 365mW. The 3.91x3.96mm2 chip is implemented in 0.5um, quad-metal, digital CMOS.

9.5 - 8b 75MSample/s 70mW Parallel Pipelined ADC Incorporating Double Sampling - 10:30 AM

W. Bright

Texas Instruments Inc., Dallas, TX

An 8b, 75MSample/s, 70mW, parallel pipelined analog-to-digital converter (ADC) uses double sampling into the residue signal path of 1.5b/stage architecture to double ADC throughput. The converter is 5.5mm2 in 3.3V 0.5um digital CMOS.

9.6 - A 5.75b, 350MSample/s or 6.75b, 150MSample/s Reconfigurable Flash ADC for a PRML Read Channel - 10:45 AM

P. Setty1, J. Barner, J. Plany, H. Burger1, J. Sonntag

Bell Labs., Lucent Technologies, Allentown, PA

1Bell Labs., Lucent Technologies, Santa Clara, CA

A reconfigurable flash ADC has a fast (350MSample/s) and a slow (150MSample/s) mode of operation with 5.75b and 6.75b of resolution. In slow mode, the converter uses 53 additional interpolating latches and two-pass encoding for an extra bit of resolution. The increase in area is <13%. The ADC is driven by a ping-pong sample/hold. In 5V BiCMOS, it has been used in a PRML read channel.

9.7 - A 400MSample/s 6b CMOS Folding and Interpolating ADC - 11:15 AM

M. P. Flynn1, now with2, B. Sheahan1

1Texas Instruments, Dallas, TX

2Silicon Systems Design, Cork, Ireland

A 6b 400MSample/s folding and interpolating CMOS ADC uses a low-impedance current-mode approach. Current division interpolation allows fast low-voltage operation. Short aperature comparators perform well without a sample-and-hold. The ADC uses a single clock and its complement, occupies 0.6mm2 in 0.5um BiCMOS and dissipates 200mW at 3.2V.

9.8 - A CMOS 6b 400MSample/s ADC with Error Correction - 11:45 AM

S. Tsukamoto, T. Endo, W. Schofield1

Fujitsu VLSI Ltd., Aichi, Japan

1Fujitsu Microelectronics, Ltd., Maidenhead, United Kingdom

A CMOS 6b 400MSample/s ADC with 3V power supply uses error correction to improve thermometer code error rates by 10,000. This ADC is fabricated in a single poly-Si, double-metal 0.35um CMOS technology.

CONCLUSION 12:00 PM

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