The tutorials introduce attendees to the state-of-the-art in integrated circuits, and give understanding of and perspective on presentations at ISSCC. Each tutorial is on a seminal topic related to the conference and is presented by an expert member of the Technical Program Committee. The 6 tutorials run in parallel sessions on Wednesday, February 4 from 8:00 AM to 3:30 PM. Each tutorial is about 90 minutes. Attendees may register for up to 3 tutorials, on a first-come, first-served basis. Attendees will be contacted and informed as to the time of their sessions. A ticket, required for admission to each tutorial, will be included in the ISSCC registration packet.
Registration: Use registration form on the Advanced Program centerfold.
High-Speed SRAM Design
Memory cell types, design and scalability. High-speed memory architecture. Fanout-dominated design techniques and decoding structures. High-speed sensing and related noise considerations. Writing circuits. Redundancy. Async vs Sync designs. Embedded arrays. Multi-port and pseudo-multi-port designs. Reliability.
Instructor: Bruce Bateman, MicroUnity Systems Engineering, Sunnyvale, CA, received the BS in EE/Materials Science & Engineering from UC Berkeley in 1976 and has been involved in memory design, primarily in high performance SRAMs and technology development. He was Manager of the SRAM design group at Cypress Semiconductor from 1983 through 1989 and has been involved in high-performance embedded memory at MicroUnity and SGI since 1992. He is currently Director of VLSI Design at MicroUnity Systems Engineering.
How a Spread-Spectrum Radio Works
Spread-Spectrum in wireless systems, including next-generation digital celluar, personal communications, and wireless local area networking. Comprehensive treatment of architecture and circuits design of complete spread-spectrum radios with RF front-end, digital modem, and network interface. Topics include wireless channel models, spread-spectrum communications, digital modem circuits, RF front-end architectures, and example systems such as IS-95.
Instructor: Charles Chien, Rockwell Science Center, received the BSEE from UC Berkeley in 1989, and MSEE and PhD from UCLA in 1991 and 1995. Since 1995 he has been with the UCLA EE Dept., where he is co-principal investigator on hand-held untethered nodes for high-performance wireless multimedia networked systems. In 1997, he joined Rockwell Science Center as Principal Scientist and Acting Manager of the Communication Systems Group. Dr. Chien has experience in digital communications, digital signal processing, high-speed CMOS circuits, and VLSI circuit implementations of communication systems.
Opamp Compensation for Low-Voltage, Mixed-Signal Designs
As power-supply voltages are reduced, trends in opamp design for mixed-signal systems are toward multiple non-cascode stages. Frequency-compensation techniques applicable to three- and four-stage amplifiers are covered. After a review of basic pole-splitting, nested Miller and nested Gm-C compensation are described. Practical CMOS designs are presented.
Instructor: John W. Fattaruso, Texas Instruments, Dallas, TX, received the PhD in EE from UC Berkeley in 1987. He has since worked in CMOS analog circuit R&D at Texas Instruments in Dallas, where he was elected Senior Member Technical Staff in 1994. He currently holds 10 patents in circuit design, and has authored or co-authored 16 journal and conference papers.
Sample Course Material -
Multistage opamp compensation root loci
FIR-1001: Architectures and Applications
FIR filter architectures, implementation trade-offs, high-speed filters, layout issues, pipelining techniques, programmable fixed-coefficient and adaptive FIRs, decision-feedback equalizers, applications in communication, examples.
Instructor: Mehdi Hatamian, Broadcom Corp., Irvine CA received the PhD in EE from the University of Michigan, Ann Arbor in 1982. From 1982 to 1991 he was with the Visual Communications Research and the VLSI Systems Research departments of AT&T Labs., where he became a Distinguished Member of Technical Staff in 1988. From 1991 to 1996 he was the Cofounder and Vice-President of Technology of Silicon Design Experts, Inc. In 1996 he joined Broadcom Corp. as Director of Digital Signal Processing Microelectronics Technology. His interests are high-speed VLSI signal processing, full-custom design, adaptive filtering and high-density deep-sub-micron CMOS design.
MEMS for the Circuit Designer
This two-part tutorial provides circuit designers with background for developing systems combining circuits and MEMS. It first reviews current and future applications, including micromachined sensors, MEMS tunable RF communication devices, microptical systems on a chip, microfluidics, and biomedical systems. It then focuses on fundamental limits of CMOS interface circuits, and their challenges and implementation. The tutorial concludes with analysis of the microgyroscope interface system and future opportunities.
Instructor: Khalil Najafi received the PhD in EE from University of Michigan in 1986. His research areas include MEMS, interface circuits, micromachining technology, telemetry circuits, and implantable biomedical microsystems. He is Associate Professor of EECS at University of Michigan.
Instructor: William Kaiser, Chairman of the UCLA EE Dept., received the PhD in Solid-State Physics from Wayne State University in 1984. His research includes development of automotive sensors and inertial microsensors. His group has demonstrated microgyroscope interface circuits, and micropower weak-inversion CMOS RF, and microsensor DSP systems.
High Speed Clocking for Large Digital ICs
Clocking for large high-speed synchronous digital designs, including clock generation, phase-locked loops, clock distribution, clock gating, skew management, skew budgeting, latch and register design, setup and hold-time, testability issues, and logic pipeline approaches, from simple register to multiphase-latch-based designs, using static and precharged logic. Clocking overhead minimization techniques necessary at clock frequencies approaching 1GHz.
Instructor: John Maneatis received the BS in EE and CS from UC Berkeley, in 1988 and the MS and PhD in EE from Stanford, in 1989 and 1994. At Stanford, his research interests included high-performance circuit design for phase-locked loops, microprocessors, data conversion, and clock recovery. Since 1994 he has been a circuit designer at Silicon Graphics, Mountain View, CA, in microprocessor design, clocking, and phase-locked loops.
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