IBM, Rochester, MN
Microprocessor microarchitectures and streamlined instruction sets are required as fundamental physical and logical limits emerge. Improved performance is expected from microprocessors exploiting high in-line programming with advanced compilers but maximizing operating frequency while maintaining short pipeline depth in simple regular designs.
Toshiba Corp., Kawasaki, Japan
Substrate-over-biasing together with gate-substrate-tie circuitry controls standby cycle and active cycle transistor leakage. Substrate-over-biasing applied to a test chip using 80nm gate-length technology results in 40ps gate delay at 0.5V supply.
University of California at Berkeley, CA
1 Logic Corp., Milpitas, CA
Scaling of CMOS gate lengths to deep-submicron increases device sensitivities to manufacturing variations. Data shows two distinct patterns for this variation that are insufficiently modeled by present methods. A method overcomes this limitation and allows accurate design validation.
Tohoku University, Sendai, Japan
An optical-interconnect parallel-processor system for Monte Carlo simulation is implemented using bare die on MCM. Optical-interconnect performance improvement is evaluated using a test system.
NTT Integrated Information & Energy Systems Labs., Kanagawa
1NTT Network Service Systems Labs., Tokyo
2NTT Electronics Co., Kanagawa, Japan
A 0.25um CMOS gate array contains 64 processing units and 8-port external RAM access control. The chip executes 10G connections per second for forward calculations and 1G connection updates per second for learning calculations and can handle a 1M-synapse network with external SRAM.
Los Alamos National Lab., NM
1 Stanford University, CA
Quantum circuits implement basic logic functions using NMR techniques. Use of micromachining technology to realize an NMR quantum co-processor integrated on a silicon chip can be expected to solve specific problems significantly faster than the fastest classical machines.
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