SESSION TP2

SALON 1-6

VIDEO AND MULTIMEDIA SIGNAL PROCESSING

Chair: K. Ganapathy, Rockwell Semiconductor, Newport Beach, CA
Associate Chair: Y. Ooi, NEC Corp., Kanagawa, Japan

2.1 - A 100mm2, 0.95W, Single-Chip MPEG2 MP@ML Video Encoder with a 128GOPS Motion Estimator and a Multi-Tasking RISC-Type Controller - 1:30 PM

E. Miyagoshi, T. Araki, T. Sayama, A. Ohtani, T. Minemaru, K. Okamoto, H. Kodama, T. Morishige, A. Watabe, K. Aoki1, T. Mitsumori, H. Imanishi, T. Jinbo, Y. Tanaka, M. Taniyama, T. Shingou, T. Fukumoto, H. Morimoto, K. Aono Matsushita Electric Industrial Co., Ltd., Osaka, Japan

1Matsushita Research Institute, Kawasaki, Japan

A single-chip MPEG2 MP@ML video encoder for consumer applications with 128GOPS motion estimator and a multi-tasking RISC controller consists of 5.5M transistors and is 100mm2 in a 0.25um CMOS. Real-time encoding is at 81MHz with 0.95W power consumption at 1.8V.

2.2 - A 1.2W Single-Chip MPEG2 MP@ML Video Encoder LSI Including Wide Search Range Motion Estimation and 81MOPS Controller - 2:00 PM

E. Ogura, M. Takashima, D. Hiranaka, T. Ishikawa, Y. Yanagita, S. Suzuki, T. Fukuda, T. Ishii

Sony Corp., Tokyo, Japan

A single-chip MPEG2 MP@ML video encoder LSI integrates 81MOPS controller and motion estimator using two adaptive algorithms (maximum search area of ˜288 horizontal and ˜96 vertical pixels) reduces computation to 0.5% of full search. The 13.7x12.4mm2 4.5M-transistor device in 0.4um CMOS dissipates 1.2W at 3.3V.

2.3 - withdrawn

BREAK 3:00 PM

2.4 - A 60mW MPEG4 Video Codec using Clustered Voltage Scaling with Variable Supply-Voltage Scheme - 3:15 PM

M. Takahashi, M. Hamada, T. Nishikawa, H. Arakida, Y. Tsuboi, T. Fujita, F. Hatori, S. Mita, K. Suzuki, A. Chiba, T. Terasawa, F. Sano, Y. Watanabe, M. Suzuki, F. Yoshiya, A. Asano, H. Momose, T. Kuroda, T. Furuyama

Toshiba Corp., Saiwai-ku, Kawasaki, Japan

A 12M-transisor 9x9mm2 MPEG4 video codec in a 0.3um CMOS triple-metal technology uses 3.3V, 2.5V, and 1.75V power supply voltages generated from an external 3.3V power supply and consumes 60mW at 30MHz. Variable VDD and Vth, clustered voltage scaling, level-shift flip-flop, conditional clocking, and local memory architecture reduce power dissipation by 70%, compared to that of a conventional design.

2.5 - 0.5um CMOS Circuits Performing OFDM Demodulation and Channel Estimation/Correction for Digital Terrestrial TV Applications - 3:45 PM

C. Del Toso, P. Combelles1, P. Penard1, P. Senn2, J-L. Sicre1, L. Lauer5, L. Soyer5, J. Galbrun3, F. Scalise4

France Telecom CNET, Grenoble/1Cesson Sevign/2Grenoble, France

3SGS-Thomson, Grenoble, France/4Agrate, Italy

5Philips Semiconductors, Limeil Brevannes, France

A 0.5um 130mm2 1.8M-transistor CMOS IC integrates a 8k-FFT in 400ns for OFDM demodulation for digital terrestrial TV based on the DVB-T standard. A 140mm2 4.5M-transistor IC performs channel estimation/correction. These ICs are included in a global chipset receiver (specified in the DVBird European project) with channel decoder and synchronization ICs.

2.6 - A Power-Efficient Single-Chip OFDM Demodulator and Channel Decoder for Multi-Media Broadcasting - 4:15 PM

J. Huisken, M. Bekooij, P. Gruijters, F. Welten

Philips Research Labs., Eindhoven, The Netherlands

The 127mm2 4.5M-transistor 0.5um mixed signal IC has 40MHz analog IF signal and performs all signal processing to demodulate and decode a DAB signal to ISO-MPEG transport stream. Including complete receiver synchronization and de-interleaving using an embedded 0.5Mb memory, the IC dissipates 150mW.

CONCLUSION 4:45 PM

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