Silicon Systems Inc., Tustin,CA/Tokyo, Japan/San Jose, CA
1Maxim Integrated Products, San Jose, CA
A BiCMOS EPR4 Read Channel IC achieves 300Mb/s data rate. The '1+D' architecture uses PR4 signals for AGC and timing recovery. FIR with LMS adaptation and fault-tolerant syncbyte detection circuitry are used.
1Maxim Integrated Products, Sunnyvale, CA
A mixed-signal implementation of a full 8-state EPR4 Viterbi detector in analog sampled-data domain uses interleaved signal processing for operation >260Mb/s in 0.8um BiCMOS and near-ideal BER improvement over PR4. The IC occupies 25mm2 and dissipates 1.6W peak power. The Viterbi detector, including the survival registers, occupies 2.5mm2.
IBM Almaden Research Center, San Jose, CA
Multilevel DFE equalizer and detector circuits operate at 540MHz for 360Mb/s user data rate with rate 2/3 (1,7) code. The equalizer uses a simple -a+D2 structure and the detector is based on a split serial-load RAM architecture. The circuits are in 0.25um CMOS and consume 21mW at 540MHz and 1.8V.
Samsung Electronics Co., Ltd., Suwon, Korea
1University of Illinois, Urbana , IL
A 0.8um CMOS IC integrates all DVD 4x speed read channel functions including a 9th-order 25MHz pulse equalizer programmable over 5 octaves with 12dB boost, and 6 delay equalizers with tunable delay of +/- 93ns for one-beam tracking error. The chip occupies 25um2 and consumes 500mW at 5V.
Hitachi, Ltd., Central Research Labs., Tokyo, Japan
A 3.3V 1W 240Mb/s EPRML read channel IC for hard-disk drives uses 0.4um CMOS. The IC features a sub-ranging look-ahead pipeline analog-to-digital converter architecture. The 3.3V CMOS analog circuit has 10-9 bit error rate at a S/N of 24dB.
Cirrus Logic, Austin, TX/1Broomfield, CO
A 0.35um read-channel IC features digital interpolation of asynchronously sampled data to perform timing recovery. ADC and FIR latency do not contribute to loop delay, moving most pulse equalization to the digital FIR. An analog BIST feature provides a calibration mode for LPF tuning and full-chip testing.
National Chiao Tung University, Hsinchu, Taiwan, R.O.C.
A Reed-Solomon product-code (RS-PC) decoder for DVD applications contains two frame buffer controllers, a (182,172) row RS decoder and a (208,192) column RS decoder. The RS decoders feature an area-efficient key equation solver using the decomposed inversionless Berlekamp-Massey algorithm. The RS-PC decoder chip supports a 4xDVD speed with off-chip frame buffers.
University of California at Davis, CA
A fully-integrated analog timing recovery circuit for PRML detectors for digital magnetic storage in 1.2um CMOS uses a sample-by-sample decision-directed MMSE algorithm and achieves phase acquisition within 100b periods at a maximum 180Mb/s. It dissipates 76mW from a single 3.3V supply and has 1.8mm2 active die. At 180Mb/s the RMS clock jitter is 15ps and peak-to-peak jitter is 97ps.
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