SESSION SP22

SALON 1-6

SRAM

Chair: K. Ishibashi, Hitachi, Ltd., Tokyo, Japan
Associate Chair: T. Wada, Mitsubishi Electric Corp., Hyogo, Japan

22.1 - Synonym Hit RAM, A 500MHz 1.5ns CMOS SRAM Macro with 576b Parallel Comparison and Parity Check Functions - 1:30 PM

T. Suzuki, K. Higeta, Y. Fujimura, H. Nambu¹, R. Yamagata², K. Yamaguchi³

Hitachi Ltd., Device Dev. Ctr., Ome, Tokyo, Japan

¹Hitachi Ltd., Central Res. Lab. Kokubunji, Tokyo, Japan

²Hitachi Ltd., General Purpose Computer Div., Kanagawa, Japan

³Hitachi ULSI Eng. Corp., Kokubunji, Tokyo, Japan

A synonym hit RAM resolves the synonym problem in large cache memories of high-performance processors. The hit RAM macro features a 500MHz CMOS SRAM macro with 576b parallel comparison and parity-check functions. Source-coupled-logic circuits enable 1.5ns access comparison.

22.2 - 64kB Sum-Addressed-Memory Cache with 1.6ns Cycle and 2.6ns Latency - 2:00 PM

R. Heald, K. Shin, V. Reddy, I-F. Kao, W. Lynch, G. Lauterbach, J. Petolino

Sun Microsystems, Palo Alto, CA

Address base-plus-offset summing is merged into the decode structure of this 64kB (512kb) 4-way set-associative cache. Combining add and access operations using delayed-reset logic and a 0.25um process allows 1.6ns cycle time and 2.6ns latency for the combined address add and cache access.

22.3 - A 3.6mW, 1.4V SRAM with Non-Boosted, Vertical Bipolar Bitline Contact Memory Cell - 2:30 PM

H. Sato, H. Nagaoka, H. Honda, Y. Maki, T. Wada, Y. Arita, K. Tsutsumi, M. Yamada

Mitsubishi Electric Corp., ULSI Lab., Hyogo, Japan

A 256kb SRAM uses a bipolar bitline contact memory cell with a large static noise margin. Minimum operating voltage is 1.4V without using a boosting technique, and access time is 60ns at 1.8V. Power dissipation is 3.6mW at 1.4V. It operates from 1.4V to 4.0V.

BREAK 3:00 PM

22.4 - A 1V 0.9mW at 100MHz 2kx16b SRAM utilizing a Half-Swing Pulsed-Decoder and Write-Bus Architecture in 0.25um Dual-Vt CMOS - 3:15 PM

T. Mori^1-2, B. Amrutur¹, K. Mai¹, M. Horowitz¹, I. Fukushi², T. Izawa³, S. Mitarai³

¹Stanford University, Stanford, CA

²Fujitsu Laboratories Ltd., Kanagawa, Japan

³Fujitsu Ltd., Kanagawa, Japan

A SRAM uses half-swing positive and negative pulses in the address predecoder to reduce decode power, and a half-Vdd bitline voltage and a half-swing write-bus to reduce write power and charge recycling to minimize half-Vdd supply current. A prototype 32kb SRAM in 0.25um dual-Vt CMOS dissipates 0.9mW at 100MHz and 1V.

22.5 - A 833Mb/s 2.5V 4Mb Double Data Rate SRAM - 3:45 PM

H-C. Park, S-K. Yang, M-C. Jung, T-G. Kang, S-C. Kim, K-M. Sohn, D-G. Bae, S-S. Kim, K-H. Kim, H-S. Kim, H-G. Byun, Y-S. Shin, H-K. Lim

Samsung Electronics Co., Ltd., Kyungki-Do, Korea

A 2.5V 4Mb double data rate SRAM in 0.25um CMOS achieves 833MHz data rate using auto-tracking read, shortened main data line, noise-immune dynamic circuit and 2b pre-fetch. Operation modes include combination of single data rate, double data rate, burst, and non-burst modes.

22.6 - A 450MHz 512kB Second-Level Cache with a 3.6GB/s Data Bandwidth - 4:15 PM

B. Bateman, C. Freeman, J. Halbert, K. Hose, G. Petrie, E. Reese

Intel Corp., Hillsboro, OR

A 450MHz 512kB 4-way set-associative cache SRAM with 3.6GB/s data rate utilizes a tightly-coupled source-synchronous 72b data bus. The 0.35um CMOS process with 0.22 um Leff provides 4 levels of metal.

22.7 - A 1.8ns Access, 550MHz, 4.5Mb CMOS SRAM - 4:45 PM

H. Nambu, K. Kanetani, K. Yamasaki, K. Higeta, M. Usami, T. Kusunoki¹, K. Yamaguchi², N. Homma³

Hitachi Ltd., Tokyo, Japan

¹Hitachi Device Eng., Co., Ltd., Chiba, Japan

²Hitachi ULSI Eng. Corp., Tokyo, Japan

³Hosei University, Tokyo, Japan

A 1.8ns, 4.5Mb CMOS SRAM achieves BiCMOS speed. It features SLC decoder with source-coupled-logic (SCL) circuits combined with reset circuits, source-follower nMOS sense amplifier and activation-pulse generator.

CONCLUSION 5:15 PM

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