SESSION SA19

SALON 8

MULTI-GIGAHERTZ SERIAL DATA

Chair: M. Nettles, AMCC, San Diego, CA
Associate Chair: T. Baba, Matsushita Semiconductor of America, Palo Alto, CA

19.1 - A 10Gb/s Si-Bipolar TX/RX Chipset for Computer Data Transmission - 8:30 AM

R. Walker, K. C. Hsieh, T. Knotts, C-S. Yen

Hewlett-Packard Labs., Palo Alto, CA

A 25GHz ft Si-bipolar transmitter/receiver chip pair uses multi-phase sampling to transmit 10Gb/s data over 20ft of 0.190in coaxial cable. The 3.0W, 2.6x4.4mm2 transmitter does clock generation and 16:1 multiplexing. The 5.5W, 3.9x4.4mm2 receiver does clock and data recovery along with 1:16 demultiplexing. Both chips use on-chip VCOs, and require a single off-chip capacitor.

19.2 - A Single Chip 2.4Gb/s CMOS Optical Receiver IC with Low Substrate Crosstalk Preamplifier - 9:00 AM

A. Tanabe, M. Soda, Y. Nakahara, A. Furukawa, T. Tamura, K. Yoshida

NEC Corp., Kanagawa, Japan

A single-chip 2.4Gb/s CMOS optical-receiver using 0.15um bulk CMOS achieves a power consumption of 104mW at 2V. A preamplifier circuit with 5.9GHz bandwidth and 59dBW gain reduces the effect of noise caused by substrate crosstalk from digital to analog parts.

19.3 - A 4.25Gb/s CMOS fiber Channel Transceiver with Asynchronous Binary Tree-Type Demultiplexer and Frequency Conversion Architecture - 9:30 AM

M. Fukaishi, K. Nakamura, M. Sato, Y. Tsutsui, S. Kishi, M. Yotsuyanagi

NEC Corp., Kanagawa, Japan

A single-chip 4.25Gb/s transceiver with an 8B/10B encoder/decoder meeting the ANSI Fiber Channel standard uses 0.25um CMOS technology. This transceiver features an asynchronous binary tree 1:8 DEMUX, a parallel-to-parallel frequency conversion, comma-detection and word-alignment logic, and operates from 3.82Gb/s to 4.43Gb/s at 2.5V.

BREAK 10:00 AM

19.4 - A Two-Chip Receiver for Short Haul Links up to 3.5Gb/s with PIN-Preamp Module and CDR-DMUX - 10:15 AM

J. Hauenschild, D. Friedrich, J. Herrle, J. Krug

Siemens AG, Munich, Germany

A 3.5Gb/s two-chip receiver consisting of a preamp and a gate-array-based CDR-DMUX uses 25GHz Si bipolar. The preamp is mounted in the PIN-diode package. Measurements show >10dB excess gain if the CDR offset is restricted. The CDR features SDH-compatible loss-of-signal detection. The chips dissipate 200mW and 1500mW respectively.

19.5 - A Jitter-Tolerant 4.5Gb/s CMOS Interconnect for Digital Display - 10:45 AM

K. Lee, S. Kim1, D-K. Jeong1, G. Kim, B. Kim, V. Da Costa, D. Lee

Silicon Image, Cupertino, CA

1National University, Seoul, Korea

A 4.5Gb/s interconnect for a digital display in 0.35um CMOS consists of three channels. Bandwidth is enough for true color SXGA (1280x1024 pixels) and beyond. Each channel supports up to 1.5Gb/s over a 10m shielded twisted-pair cable. Jitter management tolerates more than 2ns jitter, typically found on a synthesized pixel clock from graphics controllers.

19.6 - 95GHz fT Self-Aligned Selective-Epitaxial SiGe HBTs with SMI Electrodes - 11:15 AM

K. Washio, E. Ohue, K. Oda, M. Tanabe1, H. Shimamoto1, T. Onai

Hitachi, Ltd., Tokyo, Japan

1Hitachi Device Engineering Co., Ltd., Tokyo, Japan

Self-aligned selective-epitaxial SiGe-base heterojunction bipolar transistors (HBTs) with self-aligned stacked metal/IDP (SMI) electrodes provide a 95GHz cutoff frequency and 8ps ECL gate delay. A 1/8 static frequency divider operates up to 50GHz.

19.7 - 40Gb/s Analog IC Chipset for Optical Receiver using SiGe HBTs - 11:30 AM

T. Masuda, K-i. Ohhata1, E. Ohue, K. Oda, M. Tanabe1, H. Shimamoto1, T. Onai, K. Washio

Hitachi, Ltd., Tokyo, Japan

1Hitachi Device Eng. Co., Ltd., Tokyo, Japan

A 40Gb/s analog chipset with 35GHz preamplifier (PRE), 31GHz automatic gain control (AGC) amplifier core, and 40Gb/s decision circuit for optical receiver uses the selective-epitaxial SiGe HBTs described in Paper 19.6. A common-base input stage for PRE, and transimpedance amplifier active load for the AGC improve bandwidth.

CONCLUSION 11:45 AM

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