SESSION SA18

SALON 7

MULTIMEDIA PROCESSORS AND ELEMENTS

Chair: S. Purcell, Chromatic Research, Sunnyvale, CA
Associate Chair: T. Arai, NEC Corporation, Kanagawa, Japan

18.1 - A 200MHz 1.2W 1.4GFLOPS Microprocessor with Graphic Operation Unit - 8:30 AM

O. Nishii, F. Arakawa, K. Ishibashi, S. Nakano, T. Shimura, K. Suzuki, M. Tachibana, Y. Totsuka, T. Tsunoda, K. Uchiyama, T. Yamada, T. Hattori, H. Maejima, N. Nakagawa, S. Narita, M. Seki, Y. Shimazaki, R. Satomura, T. Takasuga¹, A. Hasegawa², et al.

Hitachi Ltd., Tokyo, Japan

¹Hitachi ULSI Engineering Corp., Tokyo, Japan

²Hitachi Microcomputer System Ltd., Tokyo, Japan

A 2-issue 58mm² microprocessor implemented with 5-metal-layer 0.25um CMOS dissipates 1.2W at 200MHz. The graphic operation unit processes seven floating operations every 5ns. The two-stage 4-way multiply and accumulate logic has 3.69ns simulated delay.

18.2 - A 1.2W, 2.16GOPS/720MFLOPS Embedded Superscalar Microprocessor for Multimedia Applications - 9:00 AM

H. Kubosawa, H. Takahashi, S. Ando, Y. Asada, A. Asato, A. Suga, M. Kimura, N. Higaki, H. Miyake, T. Sato, H. Anbutsu, T. Tsuda, T. Yoshimura¹, I. Amano¹, M. Kai¹, S. Mitarai¹

Fujitsu Laboratories, Ltd., Atsugi, Japan

¹Fujitsu Ltd., Atsugi, Japan

An embedded superscalar microprocessor on 9.84x10.12mm² die uses a 0.21um, 1.8V, 4-layer-metal CMOS process. A single instruction stream multiple data stream architecture and media instructions realize MPEG2 (MP@ML) decoding.

18.3 - An 800MOPS 110mW 1.5V Parallel DSP for Mobile Multimedia Processing - 9:30 AM

H. Igura, S. Narita, Y. Naito, K. Kazama, I. Kuroda, M. Motomura, M. Yamashina

NEC Corp., Kanagawa, Japan

A DSP achieves 800MOPS at 110mW (1.5V) through task-parallel processing on 4 DSP cores. The parallel architecture, including data sharing and synchronization mechanisms, is hardware- and power-efficient for portable multimedia applications. The 9.2mm² die contains 5.2M transistors with 0.25um CMOS process.

BREAK 10:00 AM

18.4 - A 667MHz RISC Microprocessor Containing a 6.0ns, 64b Integer Multiplier - 10:15 AM

A. Jain, et al.

Digital Semiconductor, Hudson, MA

A quad-issue 667MHz RISC microprocessor contains 6.0ns 26b partially-pipelined integer multiplier, 32kB, 2-way set-associative instruction cache, 16kB, dual-read-ported, data cache, advanced branch prediction, and PLL. The 6.0M transistor chip on a 6.7x15mm² die in 2.0V, 0.28um CMOS with 4 metal layers supports 2.5V I/O.

18.5 - A 2.7ns 0.25um CMOS 54x54b Multiplier - 10:45 AM

Y. Hagihara, S. Inui, A. Yoshikawa, S. Nakazato, S. Iriki, R. Ikeda, Y. Shibue, T. Inaba, M. Kagamihara, M. Yamashina

NEC Corp., Kanagawa, Japan

A 2.7ns-latency 54x54b multiplier in 4-layer-metal 0.25um CMOS uses dual-rail logic, domino circuitry, and pass transistor circuits. The multiplier targets 400MHz x 2-cycle floating point unit (FPU), and includes 135,318 transistors in 3.15mm².

18.6 - A 300MHz RISC CPU with Attached Media Processor - 11:15 AM

S. Santhanam, A. Baum, D. Bertucci, M, Braganza, K. Broch, T. Broch, J. Burnette, E. Chang, K. Chui, D. Dobberpuhl, P. Donahue, J. Grodstein, I. Kim, D. Murray, M. Pearce, A. Silveria, D. Souydalay, A. Spink, R. Stepanian, A. Varadharajan, et al.

Digital Equipment Corp., Palo Alto, CA

A 2BOPS/600MFLOPS (peak) CPU with attached media processor for video and audio signal processing has 2 16kB caches, 2 prefetch buffers and 1kB mini-cache that connect to 500MB/s on-chip SDRAM controller, 15 DMA channels. The processor uses 1.5-2.0V and 0.28um CMOS, has 3.3M transistors on a 61mm² die and dissipates 0.5-2.5W.

CONCLUSION 11:45 AM

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